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Binary Counters. 7493 Datasheet

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Binary Counters. 7493 Datasheet
















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Part

7493

Description

Decade and Binary Counters



Feature


DM7490A, DM7493A Decade and Binary Count ers March 1998 DM7490A, DM7493A Decad e and Binary Counters General Descript ion Each of these monolithic counters c ontains four master-slave flip-flops an d additional gating to provide a divide -by-two counter and a three-stage binar y counter for which the count cycle len gth is divide-by-five for the 90A and d ivide-by-eight for.
Manufacture

Fairchild

Datasheet
Download 7493 Datasheet


Fairchild 7493

7493; the 93A. All of these counters have a g ated zero reset and the 90A also has ga ted set-to-nine inputs for use in BCD n ine’s complement applications. To use their maximum count length (decade or four-bit binary), the B input is connec ted to the QA output. The input count p ulses are applied to input A and the ou tputs are as described in the appropri ate truth table. A s.


Fairchild 7493

ymmetrical divide-by-ten count can be ob tained from the 90A counters by connect ing the QD output to the A input and ap plying the input count to the B input w hich gives a divide-by-ten square wave at output QA. Features n Typical power dissipation — 90A 145 mW — 93A 130 mW n Count frequency 42 MHz Connection Diagrams Dual-In-Line Package Dual-I n-Line Package DS0065.


Fairchild 7493

33-1 Order Number DM5490J, DM5490W or DM 7490AN See Package Number J14A, N14A or W14B DS006533-2 Order Number DM7493AN See Package Number N14A © 1998 Fairc hild Semiconductor Corporation DS006533 www.fairchildsemi.com Absolute Maxim um Ratings (Note 1) Supply Voltage Inp ut Voltage Operating Free Air Temperatu re Range 7V 5.5V DM54 DM74 Storage Te mperature Range −5.





Part

7493

Description

Decade and Binary Counters



Feature


DM7490A, DM7493A Decade and Binary Count ers March 1998 DM7490A, DM7493A Decad e and Binary Counters General Descript ion Each of these monolithic counters c ontains four master-slave flip-flops an d additional gating to provide a divide -by-two counter and a three-stage binar y counter for which the count cycle len gth is divide-by-five for the 90A and d ivide-by-eight for.
Manufacture

Fairchild

Datasheet
Download 7493 Datasheet




 7493
March 1998
DM7490A, DM7493A
Decade and Binary Counters
General Description
Each of these monolithic counters contains four
master-slave flip-flops and additional gating to provide a
divide-by-two counter and a three-stage binary counter for
which the count cycle length is divide-by-five for the 90A and
divide-by-eight for the 93A.
All of these counters have a gated zero reset and the 90A
also has gated set-to-nine inputs for use in BCD nine’s
complement applications.
To use their maximum count length (decade or four-bit bi-
nary), the B input is connected to the QA output. The input
count pulses are applied to input A and the outputs are as
described in the appropriate truth table. A symmetrical
divide-by-ten count can be obtained from the 90A counters
by connecting the QD output to the A input and applying the
input count to the B input which gives a divide-by-ten square
wave at output QA.
Features
n Typical power dissipation
— 90A 145 mW
— 93A 130 mW
n Count frequency 42 MHz
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
DS006533-1
Order Number DM5490J, DM5490W
or DM7490AN
See Package Number J14A, N14A or W14B
DS006533-2
Order Number DM7493AN
See Package Number N14A
© 1998 Fairchild Semiconductor Corporation DS006533
www.fairchildsemi.com




 7493
Absolute Maximum Ratings (Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
7V
5.5V
DM54
DM74
Storage Temperature Range
−55˚C to +125˚C
0˚C to +70˚C
−65˚C to +150˚C
Recommended Operating Conditions
Symbol
Parameter
DM5490
DM7490A
Units
Min Nom Max Min Nom Max
VCC Supply Voltage
VIH High Level Input Voltage
VIL Low Level Input Voltage
IOH High Level Output Current
IOL Low Level Output Current
fCLK Clock Frequency
A
(Note 6)
B
4.5 5
5.5 4.75 5 5.25
V
22
V
0.8 0.8 V
−0.8
−0.8
mA
16 16 mA
0 32 0
32 MHz
0 16 0
16
tW Pulse Width
(Note 6)
A
B
15 15
30 30
ns
Reset
15
15
tREL Reset Release Time (Note 6)
25 25
ns
TA Free Air Operating Temperature
−55 125 0
70 ˚C
Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these
limits. The parametric values defined in the “Electrical Characteristics” table are not guaranteed at the absolute maximum ratings. The “Recommended Operating
Conditions” table will define the conditions for actual device operation.
’90A Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
(Note 2)
VI
Input Clamp Voltage
VCC = Min, II = −12 mA
VOH High Level Output VCC = Min, IOH = Max
Voltage
VIL = Max, VIH = Min
VOL Low Level Output
VCC = Min, IOL = Max
Voltage
VIH = Min, VIL = Max (Note 5)
II
Input Current @ Max
VCC = Max, VI = 5.5V
−1.5
V
2.4 3.4
V
0.2 0.4 V
1 mA
Input Voltage
IIH High Level Input VCC = Max
Current
VI = 2.7V
A
Reset
80
40 µA
B 120
IIL Low Level Input
Current
VCC = Max
VI = 0.4V
A
Reset
−3.2
−1.6
mA
B −4.8
IOS Short Circuit
VCC = Max
DM54
−20
−57 mA
Output Current
(Note 3)
DM74
−18
−57
ICC Supply Current
VCC = Max (Note 4)
29 42 mA
Note 2: All typicals are at VCC = 5V, TA = 25˚C.
Note 3: Not more than one output should be shorted at a time.
Note 4: ICC is measured with all outputs open, both RO inputs grounded following momentary connection to 4.5V, and all other inputs grounded.
Note 5: QA outputs are tested at IOL = Max plus the limit value of IIL for the B input. This permits driving the B input while maintaining full fan-out capability.
Note 6: TA = 25˚C and VCC = 5V.
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2




 7493
’90A Switching Characteristics
at VCC = 5V and TA = 25˚C
Symbol
Parameter
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPHL
Maximum Clock
Frequency
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
Low to High Level Output
Propagation Delay Time
High to Low Level Output
Propagation Delay Time
High to Low Level Output
From (Input)
To (Output)
A to QA
B to QB
A to QA
A to QA
A to QD
A to QD
B to QB
B to QB
B to QC
B to QC
B to QD
B to QD
SET-9 to
QA, QD
SET-9 to
QB, QC
SET-0
Any Q
RL = 400
CL = 15 pF
Min Max
32
16
16
18
48
50
16
21
32
35
32
35
30
40
40
Recommended Operating Conditions
Symbol
Parameter
VCC Supply Voltage
VIH High Level Input Voltage
VIL Low Level Input Voltage
IOH High Level Output Current
IOL Low Level Output Current
fCLK Clock Frequency
A
(Note 11)
B
tW Pulse Width
(Note 11)
A
B
Reset
tREL Reset Release Time (Note 11)
TA Free Air Operating Temperature
DM7493A
Min Nom Max
4.75 5 5.25
2
0.8
−0.8
16
0 32
0 16
15
30
15
25
0 70
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
V
V
V
mA
mA
MHz
ns
ns
˚C
3 www.fairchildsemi.com




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