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Output Disable. ADP3418 Datasheet

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Output Disable. ADP3418 Datasheet






ADP3418 Disable. Datasheet pdf. Equivalent




ADP3418 Disable. Datasheet pdf. Equivalent





Part

ADP3418

Description

Dual Bootstrapped 12 V MOSFET Driver with Output Disable



Feature


Dual Bootstrapped 12 V MOSFET Driver wit h Output Disable ADP3418 FEATURES All-I n-One Synchronous Buck Driver Bootstrap ped High-Side Drive 1 PWM Signal Genera tes Both Drives Anticross-Conduction Pr otection Circuitry Output Disable Contr ol Turns Off Both MOSFETs to Float Outp ut per Intel® VRM 10 Specification APP LICATIONS Multiphase Desktop CPU Suppli es Single-Supply Sy.
Manufacture

Analog Devices

Datasheet
Download ADP3418 Datasheet


Analog Devices ADP3418

ADP3418; nchronous Buck Converters GENERAL DESCRI PTION IN FUNCTIONAL BLOCK DIAGRAM VCC 4 BST 1 2 8 DRVH 7 SW OVERLAP PROT ECTION CIRCUIT The ADP3418 is a dual h igh voltage MOSFET driver optimized for driving two N-channel MOSFETs, which a re the two switches in a nonisolated sy nchronous buck power converter. Each of the drivers is capable of driving a 30 00 pF load with a .


Analog Devices ADP3418

20 ns propagation delay and a 30 ns tran sition time. One of the drivers can be bootstrapped and is designed to handle the high voltage slew rate associated w ith floating high-side gate drivers. Th e ADP3418 includes overlapping drive pr otection to prevent shoot-through curre nt in the external MOSFETs. The OD pin shuts off both the high-side and the lo w-side MOSFETs to .


Analog Devices ADP3418

prevent rapid output capacitor discharge during system shutdown. The ADP3418 is specified over the commercial temperat ure range of 0°C to 85°C and is avail able in a thermally enhanced 8-lead SOI C package. OD 3 5 DRVL ADP3418 6 PG ND 12V VCC 4 D1 BST 1 CBST CVCC AD P3418 IN DRVH 8 SW 7 TO INDUCTOR DELAY +1V DRVL 5 1V OD 3 6 PGND Q2 Q1 Figur e 1. General Applica.

Part

ADP3418

Description

Dual Bootstrapped 12 V MOSFET Driver with Output Disable



Feature


Dual Bootstrapped 12 V MOSFET Driver wit h Output Disable ADP3418 FEATURES All-I n-One Synchronous Buck Driver Bootstrap ped High-Side Drive 1 PWM Signal Genera tes Both Drives Anticross-Conduction Pr otection Circuitry Output Disable Contr ol Turns Off Both MOSFETs to Float Outp ut per Intel® VRM 10 Specification APP LICATIONS Multiphase Desktop CPU Suppli es Single-Supply Sy.
Manufacture

Analog Devices

Datasheet
Download ADP3418 Datasheet




 ADP3418
Dual Bootstrapped 12 V MOSFET
Driver with Output Disable
ADP3418
FEATURES
All-In-One Synchronous Buck Driver
Bootstrapped High-Side Drive
1 PWM Signal Generates Both Drives
Anticross-Conduction Protection Circuitry
Output Disable Control Turns Off Both MOSFETs to
Float Output per Intel® VRM 10 Specification
APPLICATIONS
Multiphase Desktop CPU Supplies
Single-Supply Synchronous Buck Converters
GENERAL DESCRIPTION
The ADP3418 is a dual high voltage MOSFET driver optimized
for driving two N-channel MOSFETs, which are the two switches
in a nonisolated synchronous buck power converter. Each of the
drivers is capable of driving a 3000 pF load with a 20 ns propa-
gation delay and a 30 ns transition time. One of the drivers can
be bootstrapped and is designed to handle the high voltage slew
rate associated with floating high-side gate drivers. The ADP3418
includes overlapping drive protection to prevent shoot-through
current in the external MOSFETs. The OD pin shuts off both
the high-side and the low-side MOSFETs to prevent rapid output
capacitor discharge during system shutdown.
The ADP3418 is specified over the commercial temperature
range of 0°C to 85°C and is available in a thermally enhanced
8-lead SOIC package.
FUNCTIONAL BLOCK DIAGRAM
VCC
4
IN 2
OVERLAP
PROTECTION
CIRCUIT
OD 3
ADP3418
BST
1
8 DRVH
7 SW
5 DRVL
6
PGND
12V
ADP3418
IN
VCC
4
1V
OD
3
DELAY
+1V
D1
BST
1
CBST
DRVH
8
SW
7
CVCC
Q1
TO INDUCTOR
DRVL
5
PGND
6
Q2
REV. 0
Figure 1. General Application Circuit
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.




 ADP3418
ADP3418–SPECIFICATIONS1
(VCC = 12 V, BST = 4 V to 26 V, TA = 0؇C to 85؇C, unless otherwise noted.)
Parameter
Symbol Conditions
SUPPLY
Supply Voltage Range
Supply Current
OD INPUT
Input Voltage High
Input Voltage Low
Input Current
Propagation Delay Time2
PWM INPUT
Input Voltage High
Input Voltage Low
Input Current
VCC
ISYS BST = 12 V, IN = 0 V
tpdlOD
tpdhOD
See Figure 2
See Figure 2
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times2
Propagation Delay2, 3
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
VBST – VSW = 12 V
VBST – VSW = 12 V
See Figure 3, VBST – VSW = 12 V,
CLOAD = 3 nF
See Figure 3, VBST – VSW = 12 V,
CLOAD = 3 nF
See Figure 3, VBST – VSW = 12 V
VBST – VSW = 12 V
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times2
Propagation Delay2, 3
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
See Figure 3, CLOAD = 3 nF
See Figure 3, CLOAD = 3 nF
See Figure 3
See Figure 3
NOTES
1All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
2AC specifications are guaranteed by characterization but not production tested.
3For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
Specifications subject to change without notice.
Min Typ Max
4.15
3
13.2
6
2.8
–1
15
20
0.8
+1
30
40
3.5
0.8
–1 +1
1.8 3.0
1.0 2.5
35 45
20 30
40 65
20 35
1.8 3.0
1.0 2.5
25 35
21 30
30 60
10 20
Unit
V
mA
V
V
µA
ns
ns
V
V
µA
ns
ns
ns
ns
ns
ns
ns
ns
–2– REV. 0




 ADP3418
ADP3418
ABSOLUTE MAXIMUM RATINGS*
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
BST . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to VCC + 15 V
BST to SW . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +15 V
SW
DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –5 V to +15 V
<200 ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . –10 V to +15 V
DRVH . . . . . . . . . . . . . . . . . . . . . . SW – 0.3 V to BST + 0.3 V
DRVL (<200 ns) . . . . . . . . . . . . . . . . . . . –2 V to VCC + 0.3 V
All Other Inputs and Outputs . . . . . . . –0.3 V to VCC + 0.3 V
Operating Ambient Temperature Range . . . . . . . . 0°C to 85°C
Operating Junction Temperature Range . . . . . . . 0°C to 150°C
Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C
Junction-to-Air Thermal Resistance (θJA)
2-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
4-Layer Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90°C/W
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Absolute maximum
ratings apply individually only, not in combination. Unless otherwise specified, all
voltages are referenced to PGND.
Model
ADP3418JR
ORDERING GUIDE
Temperature Range
0°C to 85°C
Package Option
RN-8 (SOIC-8)
PIN CONFIGURATION
RN-8
BST 1
IN 2
ADP3418
8 DRVH
7 SW
OD 3 TOP VIEW 6 PGND
(Not to Scale)
VCC 4
5 DRVL
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds
this bootstrapped voltage for the high-side MOSFET as it is switched. The capacitor should be chosen between
100 nF and 1 µF.
2 IN
Logic Level Input. This pin has primary control of the drive outputs.
3 OD
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
4 VCC Input Supply. This pin should be bypassed to PGND with ~1 µF ceramic capacitor.
5
DRVL
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
6
PGND
Power Ground. Should be closely connected to the source of the lower MOSFET.
7 SW
This pin is connected to the buck-switching node, close to the upper MOSFET’s source. It is the floating
return for the upper MOSFET drive signal. It is also used to monitor the switched voltage to prevent turn-on of
the lower MOSFET until the voltage is below ~1 V. Thus, according to operating conditions, the high-low
transition delay is determined at this pin.
8
DRVH
Buck Drive. Output drive for the upper (buck) MOSFET.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADP3418 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. 0
–3–



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