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MM74C02N. 74C02N Datasheet

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MM74C02N. 74C02N Datasheet






74C02N MM74C02N. Datasheet pdf. Equivalent




74C02N MM74C02N. Datasheet pdf. Equivalent





Part

74C02N

Description

MM74C02N



Feature


MM74C00 • MM74C02 • MM74C04 Quad 2-I nput NAND Gate • Quad 2-Input NOR Gat e • Hex Inverter October 1987 Revise d January 1999 MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Qua d 2-Input NOR Gate • Hex Inverter Ge neral Description The MM74C00, MM74C02, and MM74C04 logic gates employ complem entary MOS (CMOS) to achieve wide power supply operating range, low power.
Manufacture

Fairchild

Datasheet
Download 74C02N Datasheet


Fairchild 74C02N

74C02N; consumption, high noise immunity and sy mmetric controlled rise and fall times. With features such as this the 74C log ic family is close to ideal for use in digital systems. Function and pin out c ompatibility with series 74 devices min imizes design time for those designers already familiar with the standard 74 l ogic family. All inputs are protected from damage due to.


Fairchild 74C02N

static discharge by diode clamps to VCC and GND. Features s Wide supply voltag e range: 3V to 15V s Guaranteed noise m argin: 1V s High noise immunity: 0.45 V CC (typ.) s Low power consumption: 10 n W/package (typ.) s Low power: TTL compa tibility: .


Fairchild 74C02N

.

Part

74C02N

Description

MM74C02N



Feature


MM74C00 • MM74C02 • MM74C04 Quad 2-I nput NAND Gate • Quad 2-Input NOR Gat e • Hex Inverter October 1987 Revise d January 1999 MM74C00 • MM74C02 • MM74C04 Quad 2-Input NAND Gate • Qua d 2-Input NOR Gate • Hex Inverter Ge neral Description The MM74C00, MM74C02, and MM74C04 logic gates employ complem entary MOS (CMOS) to achieve wide power supply operating range, low power.
Manufacture

Fairchild

Datasheet
Download 74C02N Datasheet




 74C02N
October 1987
Revised January 1999
MM74C00 • MM74C02 • MM74C04
Quad 2-Input NAND Gate •
Quad 2-Input NOR Gate •
Hex Inverter
General Description
The MM74C00, MM74C02, and MM74C04 logic gates
employ complementary MOS (CMOS) to achieve wide
power supply operating range, low power consumption,
high noise immunity and symmetric controlled rise and fall
times. With features such as this the 74C logic family is
close to ideal for use in digital systems. Function and pin
out compatibility with series 74 devices minimizes design
time for those designers already familiar with the standard
74 logic family.
All inputs are protected from damage due to static dis-
charge by diode clamps to VCC and GND.
Features
s Wide supply voltage range: 3V to 15V
s Guaranteed noise margin: 1V
s High noise immunity: 0.45 VCC (typ.)
s Low power consumption: 10 nW/package (typ.)
s Low power: TTL compatibility:
Fan out of 2 driving 74L
Ordering Code:
Order Number Package Number
Package Description
MM74C00M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C00N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
MM74C02N
MM74C04M
MM74C04N
M14A
M14A
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C00
MM74C02
Top View
MM74C04
Top View
Top View
© 1999 Fairchild Semiconductor Corporation DS005877.prf
www.fairchildsemi.com




 74C02N
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
Operating Temperature Range
Storage Temperature Range
Operating VCC Range
Maximum VCC Voltage
Power Dissipation (PD)
Dual-In-Line
Small Outline
0.3V to VCC + 0.3V
40°C to +85°C
65°C to +150°C
3.0V to 15V
18V
700 mW
500 mW
Lead Temperature
(Soldering, 10 seconds)
300°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across the guaranteed temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
VIN(1)
Logical “1” Input Voltage
VIN(0)
Logical “0” Input Voltage
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
IIN(1)
Logical “1” Input Current
IIN(0)
Logical “0” Input Current
ICC Supply Current
LOW POWER TO CMOS
VIN(1)
Logical “1” Input Voltage
VIN(0)
Logical “0” Input Voltage
VOUT(1)
Logical “1” Output Voltage
VOUT(0)
Logical “0” Output Voltage
CMOS TO LOW POWER
VIN(1)
VIN(0)
VOUT(1)
VOUT(0)
Logical “1” Input Voltage
Logical “0” Input Voltage
Logical “1” Output Voltage
Logical “0” Output Voltage
VCC = 5.0V
VCC = 10V
VCC = 5.0V
VCC = 10V
VCC = 5.0V, IO = −10 µA
VCC = 10V, IO = −10 µA
VCC = 5.0V, IO = 10 µA
VCC = 10V, IO = 10 µA
VCC = 15V, VIN = 15V
VCC = 15V, VIN = 0V
VCC = 15V
74C, VCC = 4.75V
74C, VCC = 4.75V
74C, VCC = 4.75V, IO = −10 µA
74C, VCC = 4.75V, IO = 10 µA
74C, VCC = 4.75V
74C, VCC = 4.75V
74C, VCC = 4.75V, IO = −360 µA
74C, VCC = 4.75V, IO = 360 µA
OUTPUT DRIVE (see Family Characteristics Data Sheet) TA = 25°C (short circuit current)
ISOURCE
ISOURCE
ISINK
ISINK
Output Source Current
Output Source Current
Output Sink Current
Output Sink Current
VCC = 5.0V, VIN(0) = 0V, VOUT = 0V
VCC = 10V, VIN(0) = 0V, VOUT = 0V
VCC = 5.0V, VIN(1) = 5.0V, VOUT = VCC
VCC = 10V, VIN(1) = 10V, VOUT = VCC
Min Typ
3.5
8.0
4.5
9.0
1.0
0.005
0.005
0.01
VCC 1.5
4.4
4.0
2.4
1.75
8.0
1.75
8.0
Max
1.5
2.0
0.5
1.0
1.0
15
0.8
0.4
1.0
0.4
Units
V
V
V
V
V
V
V
V
µA
µA
µA
V
V
V
V
V
V
V
V
mA
mA
mA
mA
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise specified
Symbol
Parameter
Conditions
Min Typ Max
Units
MM74C00, MM74C02, MM74C04
tpd0, tpd1
Propagation Delay Time to
VCC = 5.0V
Logical “1” or “0”
VCC = 10V
CIN Input Capacitance
(Note 3)
CPD
Power Dissipation Capacitance
Per Gate or Inverter (Note 4)
Note 2: AC Parameters are guaranteed by DC correlated testing.
50 90
30 60
6.0
12
ns
ns
pF
pF
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note—
AN-90.
www.fairchildsemi.com
2




 74C02N
Typical Performance Characteristics
Gate Transfer Characteristics
Propagation Delay vs
Ambient Temperature
MM74C00, MM74C02, MM74C04
Guaranteed Noise Margin
Over Temperature vs VCC
Propagation Delay vs
Ambient Temperature
MM74C00, MM74C02, MM74C04
Power Dissipation vs Frequency
MM74C00, MM74C02, MM74C04
Propagation Delay Time vs
Load Capacitance
MM74C00, MM74C02, MM74C04
3 www.fairchildsemi.com






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