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Image Sensor. CCD133A Datasheet

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Image Sensor. CCD133A Datasheet
















CCD133A Sensor. Datasheet pdf. Equivalent













Part

CCD133A

Description

1024 Element High Speed Linear Image Sensor



Feature


www.DataSheet4U.com CCD 133A 1024-Eleme nt High Speed Linear Image Sensor FEATU RES • • • • • • • • • 1024 x 1 photosite array 13 µm x 13 µm photosites on 13µm pitch High speed: up to 20 MHz data rate Enhanced spectral response Low dark signal High responsivity On-chip clock drivers Dyn amic range typical: 7500:1 Over 1 V pea k-to-peak outputs Special selections avai.
Manufacture

Fairchild Imaging

Datasheet
Download CCD133A Datasheet


Fairchild Imaging CCD133A

CCD133A; lable – consult factory GENERAL DESCR IPTION The CCD133A is a 1024-photoeleme nt linear image sensor utilizing charge -coupled device technology. It is desig ned for visible and very-near-IR imagin g applications such as page scanning, f acsimile, optical character recognition , earth-resources-satellite telescopes, at the user’s option by supplying in put voltages and wave .


Fairchild Imaging CCD133A

and other applications which require hig h resolution, forms different than thos e required for standard high responsivi ty, high data rates, and high dynamic C CD133-type operation. range. DataSheet4 U.com Photoelement size is 13 µm (0.51 mils) x 13 µm (0.51 The CCD133A has be en improved and is pin-for-pin mils) on 13 µm (0.51 mils) centers. The device s are compatible with.


Fairchild Imaging CCD133A

the CCD133 except for the deletion of m anufactured using Fairchild Imaging’s advanced secthe end-of-Scan Waveform ( EOSOUT). The CCD133A ond-generation n-c hannel Isoplanar buried-channel has sev eral new features which may be implemen ted technology. e DataShe DataSheet4U .com Fairchild Imaging, Inc., 1801 McC arthy Blvd., Milpitas, CA 95035 • (80 0)325-6975 • (408) 433.





Part

CCD133A

Description

1024 Element High Speed Linear Image Sensor



Feature


www.DataSheet4U.com CCD 133A 1024-Eleme nt High Speed Linear Image Sensor FEATU RES • • • • • • • • • 1024 x 1 photosite array 13 µm x 13 µm photosites on 13µm pitch High speed: up to 20 MHz data rate Enhanced spectral response Low dark signal High responsivity On-chip clock drivers Dyn amic range typical: 7500:1 Over 1 V pea k-to-peak outputs Special selections avai.
Manufacture

Fairchild Imaging

Datasheet
Download CCD133A Datasheet




 CCD133A
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CCD 133A
1024-Element High Speed
Linear Image Sensor
FEATURES
1024 x 1 photosite array
13 µm x 13 µm photosites on 13µm pitch
High speed: up to 20 MHz data rate
Enhanced spectral response
Low dark signal
High responsivity
On-chip clock drivers
Dynamic range typical: 7500:1
Over 1 V peak-to-peak outputs
Special selections available – consult factory
GENERAL DESCRIPTION
The CCD133A is a 1024-photoelement linear image
sensor utilizing charge-coupled device technology. It
is designed for visible and very-near-IR imaging appli-
cations such as page scanning, facsimile, optical char-
acter recognition, earth-resources-satellite telescopes,
at the user’s option by supplying input voltages and wave
and other applications which require high resolution,
forms different than those required for standard
high responsivity, high data rates, and high dynamic
CCD133-type operation.
range.
DataSheet4U.com
Photoelement size is 13 µm (0.51mils) x 13 µm (0.51
The CCD133A has been improved and is pin-for-pin
mils) on 13 µm (0.51 mils) centers. The devices are
compatible with the CCD133 except for the deletion of
manufactured using Fairchild Imaging’s advanced sec-
the end-of-Scan Waveform (EOSOUT). The CCD133A
ond-generation n-channel Isoplanar buried-channel
has several new features which may be implemented
technology.
DataShee
DataSheet4U.com
Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
DataSheet4 U .com




 CCD133A
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CCD133A
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FUNCTIONAL DESCRIPTION
The CCD133A consists of the following functional elements illus-
trated in the Block Diagram and Circuit Diagram (Fig1.).
charge packets from “A” and “B” shift registers to their amplifiers so
that the original serial sequential string of video information may be
easily demutiplexed off-chip.
Photosites: A row of
a diffused channel stop
1024
and
image sensor
covered by a
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Reset Gates: Each transport
packets to a precharged diode.
ana-
The
passivation layer. Image photons pass through the transparent sili-
change in diode potential is linearly proportional to the amount of
con creating hole-electron pairs. The photon generated electrons
charge delivered in the charge packet. This potential is applied to the
are accumulated in the photosites. The amount of charge accumu-
input gate of a MOS transistor amplifier (see below), which linearly
lated in each photosite is a linear function of the incident illumination
amplifies the input potential. The diode is reset to the reset drain
intensity and the integration period. The output signal will vary in an
bias voltage (VRD) by the reset gate structure. Reset occurs when
analog manner from a thermally generated background level at zero
both the internal reset clocks (φT on the “A: side, φT on the “B” side)
illumination to a maximum at saturation under bright illumination.
are “High.” Each side is reset just before the next charge packet is
delivered from its respective transport analog shift register.
Photogate: The photogate structure, located at the edge of the
photosites, provides a bias voltage for the photosites.
Output Amplifiers and Sample-and Hold Gates: Each sides’
gated charge integrator drives the input of a two-stage linear MOS-
Transfer Gate: The transfer gate structure separates the outer
edge of the photogates from the analog shift registers. Charge-
packets generated and accumulated in the photosites are transferred
into the transport analog shift registers whenever the transfer gate
voltage goes “High”. All odd-numbered charge packets are trans-
ferred into the “A” transport analog shift register: all even-numbered
charge packets are transferred into the “B” transport analog shift
register. The transfer gate also controls the input of charge from VEI
into the white reference cells (described below). The time interval
between successive transfer pulses determines the integration time.
transistor amplifier. A schematic diagram of this circuit is shown in
Figure 9 below. The two stages of each amplifier are separated by
sample-and-hold gates. The output of the first stage is connected to
the input of the second stage whenever the sample-and-hold gates is
“High”. The output of the second stage is connected to the VIDEOOUT
pin. The sample-and-hold gates are switching MOS transistors: clock-
ing these gates results in a sampled-and-held output, thus eliminat-
ing the reset clock feedthrough. When on-chip sample-and-hold is
used, pin 2 is to be tied to pin 3 and pin 21 is to be tied to pin 22. Off-
chip sample-and hold pulses can be supplied through pins 2 and 22.
The sample-and-hold operation can be disabled by tying pins 2 and
Analog Shift Registers: Four 529-element analog shift regis-
ters transport charge towards the output end of the chip. the two
22 to VDD. Whenever on-chip sample-and hold is not used, pins 3
and 21 should be left unconnected.
inner registers, the transport registers, move the image generated
charge packets serially to the two gated charge detectors and am-
plifiers. The two outer shift registers, the peripheral registers, accu-
mulate charge generated at the chip periphery (by photons passing
through unavoidable gaps in the light shield layer, etc.) and trans-
port it to charge sinks. The primary shift register clock is φT. The
Clock Driver Circuits: Two MOSFET clock-driver circuits on-
chip allow sample-and-held operation of the CCD133A with only two
externally-supplied clocks: the square-wave primary shift register
transport clock φT, which determines the output data rate, and the
transfer clock φX, which determines the integration time.
complementary phase relationship of the secondary shift register
clocks φT and φT, generated on-chip, provide alternate delivery of
Dark Reference Circuitry: Four additional sensing elements at
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Fairchild Imaging, Inc., 1801 McCarthy Blvd., Milpitas, CA 95035 • (800)325-6975 • (408) 433-2500
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 CCD133A
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CCD133A
both ends of the 1024-photosite array are covered by opaque metal-
lization. These “Dark Reference Cells” provide four charge packets
(two on each side) at each end of the serial video output which indi-
cate the typical dark (non-illuminated) signal level. These cells may
be used as inputs to external DC restoration.
DEFINITION OF TERM
Charge Transfer Efficiency Percentage of valid charge in-
formation that is transferred between each successive stage of the
transport registers.
Responsivity The output signal voltage per unit exposure for a
specified spectral type of radiation. Responsivity equals output volt-
age divided by exposure.
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Charge-Coupled Device A Charge-coupled device is a semi-
conductor device in which finite isolated charge-packets are trans-
ported from one position in the semiconductor to an adjacent posi-
tion by sequential clocking of an array of gates. The charge-packets
are minority carriers with respect to the semiconductor substrate.
Total Photoresponse Non-uniformity The difference of the
response levels of the most and the least sensitive element under
uniform illumination. Measurement of PRNU excludes first and last
elements.
Dark Signal The output signal in the dark caused by thermally
Transfer Clock φX The transfer clock is the voltage waveform
generated electrons that is a linear function of the integration time
applied to the transfer gate to move the accumulated charge from
and highly sensitive to temperature. (See accompanying photos for
the image sensor elements to the CCD transport shift registeDrsa. taSheet4Ud.ectoamils of definition.)
DataShee
Transport Clock φT The transport clock is the clock applied to
the gates of the CCD transport shift registers to move the charge-
packets received from the image sensor elements to the gate charge-
detector/amplifiers.
Sample-and-Hold Clock (φSHCA, φSHCB) The voltage wave-
form applied to the sample-and-hold gates in the output amplifiers
to create a continuous sampled video signal at the output. The
sample-and-hold feature may be defeated by connecting φSHGA and
φSHGA to VDD.
Saturation Output Voltage The maximum usable signal out-
put voltage. Charge transfer efficiency decreases sharply when the
saturation output voltage is exceeded.
Integration Time The time interval between the falling edge of
any two successive transfer pulses (φX). The integration is the time
allowed for the photosites to collect charge.
Pixel - A picture element (photosite).
Isolation Cell A site on-chip producing an element in the video
output that serves as a buffer between valid video data and dark
reference signals. The output from an isolation cell contains no
valid information and should be ignored.
Dynamic Range The saturation exposure divided by the rms
temporal noise equivalent exposure. Dynamic range is sometimes
defined in terms of peak-to-peak noise. To compare the two defini-
tions a factor of four to six is generally appropriate in that peak-to-
peak noise is approximately equal to four to six times rms noise.
RMS Noise Equivalent Exposure The exposure level that
gives an output signal to the rms noise level at the output in the
dark.
Saturation Exposure The minimum exposure level that will
provide a saturation output signal. Exposure is equal to the light
intensity times the photosites integration time.
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