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DM74AS169A. 74AS169 Datasheet

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DM74AS169A. 74AS169 Datasheet
















74AS169 DM74AS169A. Datasheet pdf. Equivalent













Part

74AS169

Description

DM74AS169A



Feature


DM74AS169A Synchronous 4-Bit Binary Up/D own Counter April 1984 Revised March 2 000 DM74AS169A Synchronous 4-Bit Binar y Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead fo r cascading in high speed counting appl ications. The DM74AS169 is a 4-bit bina ry up/down counter. The carry output is decoded to preven.
Manufacture

ETC

Datasheet
Download 74AS169 Datasheet


ETC 74AS169

74AS169; t spikes during normal mode of counting operation. Synchronous operation is pro vided so that outputs change coincident with each other when so instructed by count enable inputs and internal gating . This mode of operation eliminates the output counting spikes which are norma lly associated with asynchronous (rippl e clock) counters. A buffered clock inp ut triggers the fo.


ETC 74AS169

ur flip-flops on the rising (positive go ing) edge of clock input waveform. Thes e counters are fully programmable; that is, the outputs may each be preset eit her HIGH or LOW. The load input circuit ry allows loading with carry-enable out put of cascaded counters. As loading is synchronous, setting up a LOW level at the load input disables the counter an d causes the outpu.


ETC 74AS169

ts to agree with the data inputs after t he next clock pulse. The carry look-ahe ad circuitry permits cascading counters for n-bit synchronous applications wit hout additional gating. Both count enab le inputs (P and T) must be LOW to coun t. The direction of the count is determ ined by the level of the up/down input. When the input is HIGH, the counter co unts UP; when LOW,.




Part

74AS169

Description

DM74AS169A



Feature


DM74AS169A Synchronous 4-Bit Binary Up/D own Counter April 1984 Revised March 2 000 DM74AS169A Synchronous 4-Bit Binar y Up/Down Counter General Description These synchronous presettable counters feature an internal carry look ahead fo r cascading in high speed counting appl ications. The DM74AS169 is a 4-bit bina ry up/down counter. The carry output is decoded to preven.
Manufacture

ETC

Datasheet
Download 74AS169 Datasheet




 74AS169
April 1984
Revised March 2000
DM74AS169A
Synchronous 4-Bit Binary Up/Down Counter
General Description
These synchronous presettable counters feature an inter-
nal carry look ahead for cascading in high speed counting
applications. The DM74AS169 is a 4-bit binary up/down
counter. The carry output is decoded to prevent spikes dur-
ing normal mode of counting operation. Synchronous oper-
ation is provided so that outputs change coincident with
each other when so instructed by count enable inputs and
internal gating. This mode of operation eliminates the out-
put counting spikes which are normally associated with
asynchronous (ripple clock) counters. A buffered clock
input triggers the four flip-flops on the rising (positive going)
edge of clock input waveform.
These counters are fully programmable; that is, the outputs
may each be preset either HIGH or LOW. The load input
circuitry allows loading with carry-enable output of cas-
caded counters. As loading is synchronous, setting up a
LOW level at the load input disables the counter and
causes the outputs to agree with the data inputs after the
next clock pulse.
The carry look-ahead circuitry permits cascading counters
for n-bit synchronous applications without additional gating.
Both count enable inputs (P and T) must be LOW to count.
The direction of the count is determined by the level of the
up/down input. When the input is HIGH, the counter counts
UP; when LOW, it counts DOWN. Input T is fed forward to
enable the carry outputs. The carry output thus enabled will
produce a LOW level output pulse with a duration approxi-
mately equal to the HIGH portion of the QA output when
counting UP, and approximately equal to the LOW portion
of the QA output when counting DOWN. This LOW level
overflow carry pulse can be used to enable successively
cascaded stages. Transitions at the enable P or T inputs
are allowed regardless of the level of the clock input.
The control functions for these counters are fully synchro-
nous. Changes at control inputs (enable P, enable T, load,
up/down) which modify the operating mode have no effect
until clocking occurs. The function of the counter (whether
enabled, disabled, loading or counting) will be dictated
solely by the conditions meeting the stable setup and hold
times.
Features
s Switching Specifications at 50 pF
s Switching Specifications guaranteed over full tempera-
ture and VCC range
s Advanced oxide-isolated, ion-implanted Schottky TTL
process
s Functionally and pin-for-pin compatible with Schottky
and low power Schottky TTL counterpart
s Improved AC performance over Schottky and low power
Schottky counterparts
s Synchronously programmable
s Internal look ahead for fast counting
s Carry output for n-bit cascading
s Synchronous counting
s Load control line
s ESD inputs
Ordering Code:
Order Number Package Number
Package Description
DM74AS169AM
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
DM74AS169AN
N16E
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2000 Fairchild Semiconductor Corporation DS006292
www.fairchildsemi.com




 74AS169
Connection Diagram
Logic Diagram
DM74AS169A
www.fairchildsemi.com
2




 74AS169
Absolute Maximum Ratings(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
Typical θJA
N Package
M Package
7V
7V
0°C to +70°C
65°C to +150°C
71.5°C/W
101.0°C/W
Note 1: The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
VCC
VIH
VIL
IOH
IOL
fCLK
tSU
tH
tWCLK
tA
Parameter
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Clock Frequency
tsetup, Set-up Time
Data; A, B, C, D
En P, En T
LOAD
thold, Hold Time
U/D
Data; A, B, C, D
En P, En T
LOAD
U/D
Width of Clock Pulse
Free Air Operating Temperature
Min
Nom
Max
Units
4.5 5 5.5 V
2V
0.8 V
2 mA
20 mA
0 75 MHz
8 ns
8 ns
8 ns
11 ns
0 ns
0 ns
0 ns
0 ns
6.7 ns
0 70 °C
Electrical Characteristics
over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C
Symbol
Parameter
Conditions
Min Typ
Max
Units
VIK Input Clamp Voltage
VOH HIGH Level
Output Voltage
VOL LOW Level
Output Voltage
VCC = 4.5V, II = −18 mA
IOH = −2 mA,
VCC = 4.5V to 5.5V
VCC = 4.5V,
IOL = 20 mA
VCC 2
0.35
1.2
0.5
II Input Current @ Max
VCC = 5.5V,
LOAD, ENT, U/D
0.2
Input Voltage
VIH = 7V
Others
0.1
IIH
HIGH Level Input Current
VCC = 5.5V,
LOAD, ENT, U/D
40
VIH = 2.7V
Others
20
IIL
LOW Level Input Current
VCC = 5.5V,
CLK, DATA, ENP
0.5
VIL = 0.4V
LOAD, ENT, U/D
1
IO (Note 2) Output Drive Current
VCC = 5.5V, VO = 2.25V
30 112
ICC Supply Current
VCC = 5.5V
46 63
Note 2: The output conditions have been chosen to produce a current that closely approximates one half of the true short circuit output current, IOS.
V
V
V
mA
µA
mA
mA
mA
3 www.fairchildsemi.com




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