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MM74C902N. 74C902N Datasheet

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MM74C902N. 74C902N Datasheet






74C902N MM74C902N. Datasheet pdf. Equivalent




74C902N MM74C902N. Datasheet pdf. Equivalent





Part

74C902N

Description

MM74C902N



Feature


MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer October 1987 Revised January 1999 MM 74C901 • MM74C902 Hex Inverting TTL B uffer • Hex Non-Inverting TTL Buffer General Description The MM74C901 and M M74C902 hex buffers employ complementar y MOS to achieve wide supply operating range, low power consumption, and high noise immunity. These buff.
Manufacture

Fairchild

Datasheet
Download 74C902N Datasheet


Fairchild 74C902N

74C902N; ers provide direct interface from PMOS i nto CMOS or TTL and direct interface fr om CMOS to TTL or CMOS operating at a r educed VCC supply. Features s Wide sup ply voltage range: 3.0V to 15V s Guaran teed noise margin: 1.0V s High noise im munity: 0.45 VCC (typ.) s TTL compatibi lity: Fan out of 2 driving standard TTL Ordering Code: Order Number Package Number Package De.


Fairchild 74C902N

scription MM74C901M M14A 14-Lead Smal l Outline Integrated Circuit (SOIC), JE DEC MS-120, 0.150” Narrow MM74C901N N14A 14-Lead Plastic Dual-In-Line Pac kage (PDIP), JEDEC MS-011, 0.300” Wid e MM74C902M M14A 14-Lead Small Outli ne Integrated Circuit (SOIC), JEDEC MS- 120, 0.150” Narrow MM74C902N N14A 14-Lead Plastic Dual-In-Line Package (P DIP), JEDEC MS-011, 0.30.


Fairchild 74C902N

0” Wide Devices also available in Tap e and Reel. Specify by appending the su ffix letter “X” to the ordering cod e. Connection Diagrams Pin Assignment s for DIP and SOIC MM74C901 MM74C902 Top View Logic Diagrams MM74C901 CMOS to TTL Inverting Buffer Top View MM74C 902 CMOS to TTL Buffer © 1999 Fairchi ld Semiconductor Corporation DS005909.p rf www.fairchildsemi.com.

Part

74C902N

Description

MM74C902N



Feature


MM74C901 • MM74C902 Hex Inverting TTL Buffer • Hex Non-Inverting TTL Buffer October 1987 Revised January 1999 MM 74C901 • MM74C902 Hex Inverting TTL B uffer • Hex Non-Inverting TTL Buffer General Description The MM74C901 and M M74C902 hex buffers employ complementar y MOS to achieve wide supply operating range, low power consumption, and high noise immunity. These buff.
Manufacture

Fairchild

Datasheet
Download 74C902N Datasheet




 74C902N
October 1987
Revised January 1999
MM74C901 • MM74C902
Hex Inverting TTL Buffer •
Hex Non-Inverting TTL Buffer
General Description
The MM74C901 and MM74C902 hex buffers employ com-
plementary MOS to achieve wide supply operating range,
low power consumption, and high noise immunity. These
buffers provide direct interface from PMOS into CMOS or
TTL and direct interface from CMOS to TTL or CMOS
operating at a reduced VCC supply.
Features
s Wide supply voltage range: 3.0V to 15V
s Guaranteed noise margin: 1.0V
s High noise immunity: 0.45 VCC (typ.)
s TTL compatibility: Fan out of 2 driving standard TTL
Ordering Code:
Order Number Package Number
Package Description
MM74C901M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C901N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide
MM74C902M
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow
MM74C902N
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagrams
Pin Assignments for DIP and SOIC
MM74C901
MM74C902
Top View
Logic Diagrams
MM74C901
CMOS to TTL Inverting Buffer
Top View
MM74C902
CMOS to TTL Buffer
© 1999 Fairchild Semiconductor Corporation DS005909.prf
www.fairchildsemi.com




 74C902N
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin
Voltage at Any Input Pin
MM74C901
MM74C902
0.3V to VCC + 0.3V
0.3V to +15V
0.3V to +15V
Storage Temperature Range (TS)
Power Dissipation (PD)
Dual-In-Line
Small Outline
Operating Temperature Range (TA)
MM74C901, MM74C902,
65°C to +150°C
700 mW
500 mW
40°C to +85°C
Operating VCC Range
Absolute Maximum VCC
Lead Temperature (TL)
(Soldering, 10 seconds)
3.0V to 15V
18V
260°C
Note 1: “Absolute Maximum Ratings” are those values beyond which the
safety of the device cannot be guaranteed. Except for “Operating Tempera-
ture Range” they are not meant to imply that the devices should be oper-
ated at these limits. The table of “Electrical Characteristics” provides
conditions for actual device operation.
DC Electrical Characteristics
Min/Max limits apply across temperature range unless otherwise noted
Symbol
Parameter
Conditions
CMOS TO CMOS
V IN(1)
Logical “1” Input Voltage
V IN(0)
Logical “0” Input Voltage
V OUT(1) Logical “1” Output Voltage
V OUT(0) Logical “0” Output Voltage
I IN(1)
Logical “1” Input Current
I IN(0)
Logical “0” Input Current
I CC Supply Current
TTL TO CMOS
V CC = 5.0V
V CC = 10V
V CC = 5.0V
V CC = 10V
V CC = 5.0V, IO = −10 µA
V CC = 10V, IO = −10 µA
V CC = 5.0V
V CC = 10V
V CC = 15V, VIN = 15V
V CC = 15V, VIN = 0V
V CC = 15V
V IN(1)
Logical “1” Input Voltage
V IN(0)
Logical “0” Input Voltage
CMOS TO TTL
V CC = 4.75V
V CC = 4.75V
V IN(1)
Logical “1” Input Voltage
MM74C901
V CC = 4.75V
MM74C902
V CC = 4.75V
V IN(0)
Logical “0” Input Voltage
MM74C901
V CC = 4.75V
MM74C902
V CC = 4.75V
V OUT(1) Logical “1” Output Voltage
V CC = 4.75V, IO = −800 µA
V OUT(0) Logical “0” Output Voltage
MM74C901
V CC = 4.75V, IO = 2.6 mA
MM74C902
V CC = 4.75V, IO = 3.2 mA
OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current)
(MM74C901)
I SOURCE
Output Source Current
(P-Channel)
I SOURCE
Output Source Current
(P-Channel)
I SINK
Output Sink Current
(N-Channel)
I SINK
Output Sink Current
(N-Channel)
(MM74C902)
V CC = 5.0V, VOUT = 0V
T A = 25°C, VIN = 0V
V CC = 10V, VOUT = 0V
T A = 25°C, VIN = 0V
V CC = 5.0V, VOUT = VCC
T A = 25°C, VIN = VCC
V CC = 5.0V, VOUT = 0.4V
T A = 25°C, VIN = VCC
Min Typ
3.5
8.0
4.5
9.0
0.005
1.0 0.005
0.05
V CC 1.5
Max
1.5
2.0
0.5
1.0
1.0
15
0.8
Units
V
V
V
V
V
V
V
V
µA
µA
µA
V
V
4.25
V CC 1.5
2.4
V
V
1.0 V
1.5 V
V
0.4 V
0.4 V
5.0 mA
20 mA
9.0 mA
3.8 mA
www.fairchildsemi.com
2




 74C902N
DC Electrical Characteristics (Continued)
Symbol
I SOURCE
I SOURCE
I SINK
I SINK
Parameter
Output Source Current
(P-Channel)
Output Source Current
(P-Channel)
Output Sink Current
(N-Channel)
Output Sink Current
(N-Channel)
Conditions
V CC = 5.0V, VOUT = 0V
T A = 25°C, VIN = VCC
V CC = 10V, VOUT = 0V
T A = 25°C, VIN = VCC
V CC = 5.0V, VOUT = VCC
T A = 25°C, VIN = 0V
V CC = 5.0V, VOUT = 0.4V
T A = 25°C, VIN = 0V
Min
Typ
Max
Units
5.0
mA
20 mA
9.0 mA
3.8 mA
AC Electrical Characteristics (Note 2)
TA = 25°C, CL = 50 pF, unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
MM74C901
t pd1 Propagation Delay Time
to a Logical “1”
t pd0 Propagation Delay Time
to a Logical “0”
C IN Input Capacitance
C PD
Power Dissipation Capacity
MM74C902
V CC = 5.0V
V CC = 10V
V CC = 5.0V
V CC = 10V
Any Input (Note 3)
Per Buffer (Note 4)
38 70 ns
22 30 ns
21 35 ns
13 20 ns
14 pF
30 pF
t pd1 Propagation Delay Time
V CC = 5.0V
to a Logical “1”
V CC = 10V
t pd0 Propagation Delay Time
V CC = 5.0V
to a Logical “0”
V CC = 10V
C IN Input Capacitance
Any Input (Note 3)
C PD
Power Dissipation Capacity
Per Buffer (Note 4)
Note 2: AC Parameters are guaranteed by DC correlated testing.
57 90 ns
27 40 ns
54 90 ns
25 40 ns
5.0 pF
50 pF
Note 3: Capacitance is guaranteed by periodic testing.
Note 4: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics application note
AN-90.
Typical Application
CMOS to TTL or CMOS at a Lower VCC
Note: VCC1 = VCC2
3 www.fairchildsemi.com



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