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Frequency Synthesizer. ADF4252 Datasheet

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Frequency Synthesizer. ADF4252 Datasheet
















ADF4252 Synthesizer. Datasheet pdf. Equivalent













Part

ADF4252

Description

Dual Fractional-N/Integer-N Frequency Synthesizer



Feature


Data Sheet Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252 FEATURES GENERAL DESCRIPTION 3.0 GHz fraction al-N/1.2 GHz integer-N 2.7 V to 3.3 V p ower supply Separate VP allows extended tuning voltage to 5 V Programmable dua l modulus prescaler RF: 4/5, 8/9 IF: 8/ 9, 16/17, 32/33, 64/65 Programmable cha rge pump currents 3-wire serial interfa ce Digital lock de.
Manufacture

Analog Devices

Datasheet
Download ADF4252 Datasheet


Analog Devices ADF4252

ADF4252; tect Power-down mode Programmable modulu s on fractional-N synthesizer Trade off noise vs. spurious performance APPLICA TIONS Base stations for mobile radio (G SM, PCS, DCS, CDMA, WCDMA) Wireless han dsets (GSM, PCS, DCS, CDMA, WCDMA) Wire less LANs Communications test equipment CATV equipment The ADF4252 is a dual fractional-N/integer-N frequency synthe sizer that can be .


Analog Devices ADF4252

used to implement local oscillators (LO) in the upconversion and downconversion sections of wireless receivers and tra nsmitters. Both the RF and IF synthesiz ers consist of a low noise digital phas e frequency detector (PFD), a precision charge pump, and a progr .


Analog Devices ADF4252

.





Part

ADF4252

Description

Dual Fractional-N/Integer-N Frequency Synthesizer



Feature


Data Sheet Dual Fractional-N/Integer-N Frequency Synthesizer ADF4252 FEATURES GENERAL DESCRIPTION 3.0 GHz fraction al-N/1.2 GHz integer-N 2.7 V to 3.3 V p ower supply Separate VP allows extended tuning voltage to 5 V Programmable dua l modulus prescaler RF: 4/5, 8/9 IF: 8/ 9, 16/17, 32/33, 64/65 Programmable cha rge pump currents 3-wire serial interfa ce Digital lock de.
Manufacture

Analog Devices

Datasheet
Download ADF4252 Datasheet




 ADF4252
Data Sheet
Dual Fractional-N/Integer-N
Frequency Synthesizer
ADF4252
FEATURES
GENERAL DESCRIPTION
3.0 GHz fractional-N/1.2 GHz integer-N
2.7 V to 3.3 V power supply
Separate VP allows extended tuning voltage to 5 V
Programmable dual modulus prescaler
RF: 4/5, 8/9
IF: 8/9, 16/17, 32/33, 64/65
Programmable charge pump currents
3-wire serial interface
Digital lock detect
Power-down mode
Programmable modulus on fractional-N synthesizer
Trade off noise vs. spurious performance
APPLICATIONS
Base stations for mobile radio (GSM, PCS, DCS, CDMA, WCDMA)
Wireless handsets (GSM, PCS, DCS, CDMA, WCDMA)
Wireless LANs
Communications test equipment
CATV equipment
The ADF4252 is a dual fractional-N/integer-N frequency
synthesizer that can be used to implement local oscillators (LO)
in the upconversion and downconversion sections of wireless
receivers and transmitters. Both the RF and IF synthesizers
consist of a low noise digital phase frequency detector (PFD), a
precision charge pump, and a programmable reference divider.
The RF synthesizer has a Σ-Δ-based fractional interpolator that
allows programmable fractional-N division. The IF synthesizer
has programmable integer-N counters. A complete phase-locked
loop (PLL) can be implemented if the synthesizer is used with
an external loop filter and voltage controlled oscillator (VCO).
Control of all the on-chip registers is via a simple 3-wire interface.
The device operates with a power supply ranging from 2.7 V to
3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
VDD1 VDD2 VDD3 DVDD VP1 VP2
RSET
ADF4252
REFERENCE
REFIN
2
DOUBLER
4-BIT
R COUNTER
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CPRF
REFOUT
MUXOUT
OUTPUT
MUX
LOCK
DETECT
CLK
DATA
LE
24-BIT
DATA
REGISTER
FRACTIONAL-N
RF DIVIDER
INTEGER-N
IF DIVIDER
RFINA
RFINB
IFINB
IFINA
2
DOUBLER
15-BIT
R COUNTER
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
CPIF
Figure 1.
AGND1 AGND2 DGND CPGND1 CPGND2
Rev. C
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 ADF4252
ADF4252* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• ADF4252 Evaluation Boards
Documentation
Application Notes
• AN-30: Ask the Applications Engineer - PLL Synthesizers
• AN-873: Lock Detect on the ADF4xxx Family of PLL
Synthesizers
Data Sheet
• ADF4252: Dual Fractional-N/Integer-N Frequency
Synthesizer Data Sheet
Software and Systems Requirements
• ADF4252 Evaluation Board Software
Tools and Simulations
• ADIsimPLL™
• ADIsimRF
• dt_ADF4x5x_Register_Configuration
Reference Materials
Product Selection Guide
• RF Source Booklet
Technical Articles
• Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 1
• Phase Locked Loops for High-Frequency Receivers and
Transmitters – Part 3
• Phase-Locked Loops for High-Frequency Receivers and
Transmitters - Part 2
Design Resources
• ADF4252 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all ADF4252 EngineerZone Discussions
Sample and Buy
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Technical Support
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 ADF4252
ADF4252
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Detailed Functional Block Diagram ............................................ 12
Theory of Operation ...................................................................... 13
Reference Input Section............................................................. 13
RF and IF Input Stage ................................................................ 13
RF INT Divider........................................................................... 13
INT, FRAC, MOD, and R Relationship ................................... 13
RF R Counter .............................................................................. 13
IF R Counter ............................................................................... 13
IF Prescaler (P/P + 1)................................................................. 14
IF A and B Counters .................................................................. 14
Pulse Swallow Function............................................................. 14
Phase Frequency Detector (PFD) and Charge Pump............ 14
MUXOUT and Lock Detect...................................................... 14
Lock Detect ................................................................................. 14
Input Shift Register..................................................................... 14
Register Maps .................................................................................. 15
Data Sheet
Register Descriptions ..................................................................... 23
RF N Divider Register (Address R0) ....................................... 23
RF R Divider Register (Address R1) ........................................ 23
RF Control Register (Address R2) ........................................... 23
Master Register (Address R3) ................................................... 24
IF N Divider Register (Address R4)......................................... 24
IF R Divider Register (Address R5) ......................................... 25
IF Control Register (Address R6)............................................. 25
Device Programming after Initial Power-Up.............................. 26
RF and IF Synthesizers Operational ........................................ 26
RF Synthesizer Operational, IF Power-Down .......................... 26
IF Synthesizer Operational, RF Power-Down .......................... 26
RF Synthesizer: An Example..................................................... 26
IF Synthesizer: An Example...................................................... 26
Modulus....................................................................................... 26
Reference Doubler and Reference Divider ............................. 26
12-Bit Programmable Modulus................................................ 26
Spurious Optimization and Fastlock ....................................... 27
Spurious Signals—Predicting Where They Appear............... 27
Prescaler....................................................................................... 27
Filter Design—ADIsimPLL....................................................... 27
Interfacing ....................................................................................... 28
ADuC812 Interface .................................................................... 28
ADSP-2181 Interface ................................................................. 28
PCB Design Guidelines for Chip Scale Package......................... 29
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Rev. C | Page 2 of 30




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