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Cache RAM. CY7C1325 Datasheet

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Cache RAM. CY7C1325 Datasheet
















CY7C1325 RAM. Datasheet pdf. Equivalent













Part

CY7C1325

Description

256K x 18 Synchronous 3.3V Cache RAM



Feature


www.DataSheet4U.com CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features β€ ’ Supports 117-MHz microprocessor cache systems with zero wait states β€’ 256K by 18 common I/O β€’ Fast clock-to-out put times β€” 7.5 ns (117-MHz version) β€’ Two-bit wrap-around counter support ing either interleaved or linear burst sequence β€’ Separate processor and con troller address strobes provid.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1325 Datasheet


Cypress Semiconductor CY7C1325

CY7C1325; es direct interface with the processor a nd external cache controller β€’ Synchr onous self-timed write β€’ Asynchronous output enable β€’ I/Os capable of 2.5β €“3.3V operation β€’ JEDEC-standard pin out β€’ 100-pin TQFP packaging β€’ ZZ β €œsleep” mode Functional Description The CY7C1325 is a 3.3V, 256K by 18 syn chronous cache RAM designed to interfac e with high-speed microprocessors wi.


Cypress Semiconductor CY7C1325

th minimum glue logic. Maximum access de lay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captu res the first address in a burst and in crements the address automatically for the rest of the burst access. The CY7C1 325 allows both an interleaved or linea r burst sequences, selected by the MODE input pin. A HIGH selects an interleav ed burst sequence,.


Cypress Semiconductor CY7C1325

while a LOW selects a linear burst sequ ence. Burst accesses can be initiated w ith the Processor Address Strobe (ADSP) or the Cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement ( ADV) input. A synchronous self-timed wr ite mechanism is provided to simplify t he write interface. A synchronous chip enable input and a.





Part

CY7C1325

Description

256K x 18 Synchronous 3.3V Cache RAM



Feature


www.DataSheet4U.com CY7C1325 256K x 18 Synchronous 3.3V Cache RAM Features β€ ’ Supports 117-MHz microprocessor cache systems with zero wait states β€’ 256K by 18 common I/O β€’ Fast clock-to-out put times β€” 7.5 ns (117-MHz version) β€’ Two-bit wrap-around counter support ing either interleaved or linear burst sequence β€’ Separate processor and con troller address strobes provid.
Manufacture

Cypress Semiconductor

Datasheet
Download CY7C1325 Datasheet




 CY7C1325
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CY7C1325
256K x 18 Synchronous
3.3V Cache RAM
Features
Functional Description
β€’ Supports 117-MHz microprocessor cache systems with
zero wait states
β€’ 256K by 18 common I/O
β€’ Fast clock-to-output times
β€” 7.5 ns (117-MHz version)
β€’ Two-bit wrap-around counter supporting either inter-
leaved or linear burst sequence
β€’ Separate processor and controller address strobes pro-
vides direct interface with the processor and external
cache controller
β€’ Synchronous self-timed write
β€’ Asynchronous output enable
β€’ I/Os capable of 2.5–3.3V operation
β€’ JEDEC-standard pinout
β€’ 100-pin TQFP packaging
β€’ ZZ β€œsleep” mode
The CY7C1325 is a 3.3V, 256K by 18 synchronous cache
RAM designed to interface with high-speed microprocessors
with minimum glue logic. Maximum access delay from clock
rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter cap-
tures the first address in a burst and increments the address
automatically for the rest of the burst access.
The CY7C1325 allows both an interleaved or linear burst se-
quences, selected by the MODE input pin. A HIGH selects an
interleaved burst sequence, while a LOW selects a linear burst
sequence. Burst accesses can be initiated with the Processor
Address Strobe (ADSP) or the Cache Controller Address
Strobe (ADSC) inputs. Address advancement is controlled by
the Address Advancement (ADV) input.
A synchronous self-timed write mechanism is provided to sim-
plify the write interface. A synchronous chip enable input and
an asynchronous output enable input provide easy control for
bank selection and output three-state control.
Logic Block Diagram
CLK
ADV
ADSC
ADSP
A[17:0]
GW
BWE
BW 1
18
BW 0
CE1
CE2
CE3
MODE
(A0,A1) 2
BURST Q0
CE COUNTER
CLR
Q1
DaADtaDRSEhSSeeQt4U1.6com
CE
D
REGISTER
16
D DQ[15:8] Q
BYTEWRITE
REGISTERS
D DQ[7:0] Q
BYTEWRITE
REGISTERS
D
CE
ENABLE
REGISTER
Q
CLK
18
256K X 18
MEMORY
ARRAY
18 18
DataShee
OE
ZZ SLEEP
CONTROL
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
Intel and Pentium are registered trademarks of Intel Corporation.
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7C1325-117
7.5
350
10.0
7C1325-100
8.0
325
10.0
7C1325-80
8.5
300
10.0
INPUT
REGISTERS
CLK
DQ[15:0]
DP[1:0]
7C1325-50
11.0
250
10.0
Cypress Semiconductor Corporation β€’ 3901 North First Street β€’ San Jose β€’ CA 95134 β€’ 408-943-2600
May 10, 2000
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 CY7C1325
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Pin Configurations
100-Lead TQFP
CY7C1325
et4U.com
BYTE1
NC
NC
NC
VDDQ
VSS
NC
NC
DQ8
DQ9
VSS
VDDQ
DQ10
DQ11
NC
VDD
NC
VSS
DQ12
DQ13
VDDQ
VSS
DQ14
DQ15
DP1
NC
VSS
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
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CY7C1325
80 A10
79 NC
78 NC
77 VDDQ
76 VSS
75 NC
74 DP0
73 DQ7
72 DQ6
71 VSS
70 VDDQ
69 DQ5
68 DQ4
67 VSS
66 NC
65 VDD
64 ZZ
63 DQ3
62 DQ2
61 VDDQ
60 VSS
59 DQ1
58 DQ0
57 NC
56 NC
55 VSS
54 VDDQ
53 NC
52 NC
51 NC
BYTE0
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 CY7C1325
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CY7C1325
Pin Descriptions
et4U.com
Pin Number Name
I/O
Description
85
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK. When asserted
Synchronous LOW, A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
84
36, 37
ADSP
A[1:0]
Input-
Synchronous
Input-
Synchronous
Address Strobe from Processor, sampled on the rising edge of CLK. When asserted
LOW, A[17:0] is captured in the address registers. A[1:0] are also loaded into the burst
counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP
is ignored when CE1 is deasserted HIGH.
A1, A0 address inputs, These inputs feed the on-chip burst counter as the LSBs as
well as being used to access a particular memory location in the memory array.
50–44,
80–82, 99,
100, 32–35
A[17:2]
Input-
Address Inputs used in conjunction with A[1:0] to select one of the 256K address
Synchronous locations. Sampled at the rising edge of the CLK, if CE1, CE2, and CE3 are sampled
active, and ADSP or ADSC is active LOW.
94, 93
83
BWS[1:0]
ADV
Input-
Synchronous
Input-
Synchronous
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes.
Sampled on the rising edge. BWS0 controls DQ[7:0] and DP0, BWS1 controls DQ[15:8]
and DP1. See Write Cycle Descriptions table for further details.
Advance input used to advance the on-chip address counter. When LOW the internal
burst counter is advanced in a burst sequence. The burst sequence is selected using
the MODE input.
87
BWE
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal
Synchronous must be asserted LOW to conduct a byte write.
88
GW
Input-
Global Write Input, active LOW. Sampled on the rising edge of CLK. This signal is
Synchronous used to conduct a global write, independent of the state of BWE and BWS[1:0]. Global
writes override byte writes.
89 CLK Input-Clock Clock inpuDt.aUtasSedhetoect4aUpt.ucroemall synchronous inputs to the device.
98
CE1
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE2 and CE3 to select/deselect the device. CE1 gates ADSP.
97
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE3 to select/deselect the device.
92
CE3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous conjunction with CE1 and CE2 to select/deselect the device.
86
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the I/O
Asynchronous pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins
are three-stated, and act as input data pins.
64
ZZ
Input-
Snooze Input. Active HIGH asynchronous. When HIGH, the device enters a low-pow-
Asynchronous er standby mode in which all other inputs are ignored, but the data in the memory
array is maintained. Leaving ZZ floating or NC will default the device into an active
state. ZZ has an internal pull down.
31
MODE
- Mode Input. Selects the burst order of the device. Tied HIGH selects the interleaved
burst order. Pulled LOW selects the linear burst order. When left floating or NC,
defaults to interleaved burst order. Mode pin has an internal pull up.
23, 22, 19,
18, 13, 12, 9,
8, 73, 72, 69,
68, 63, 62,
59, 58
DQ[15:0]
I/O-
Synchronous
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in
the memory location specified by A[17:0] during the previous clock rise of the read
cycle. The direction of the pins is controlled by OE in conjunction with the internal
control logic. When OE is asserted LOW, the pins behave as outputs. When HIGH,
DQ[15:0] and DP[1:0] are placed in a three-state condition. The outputs are automat-
ically three-stated when a WRITE cycle is detected.
74, 24
DP[1:0]
I/O- Bidirectional Data Parity lines. These behave identical to DQ[15:0] described above.
Synchronous These signals can be used as parity bits for bytes 0 and 1 respectively.
15, 41, 65, VDD
91
Power Supply Power supply inputs to the core of the device. Should be connected to 3.3V power
supply.
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