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OC-48 Transceiver. CYS25G0101DX Datasheet

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OC-48 Transceiver. CYS25G0101DX Datasheet
















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Part

CYS25G0101DX

Description

SONET OC-48 Transceiver



Feature


CYS25G0101DX SONET OC-48 Transceiver SO NET OC-48 Transceiver Features ■ SONE T OC-48 operation ■ Bellcore and ITU jitter compliance ■ 2.488 GBaud seria l signaling rate ■ Multiple selectabl e loopback or loop through modes ■ Si ngle 155.52 MHz reference clock ■ Tra nsmit FIFO for flexible data interface clocking ■ 16-bit parallel-to-serial conversion in transmit path ■ Se.
Manufacture

Cypress Semiconductor

Datasheet
Download CYS25G0101DX Datasheet


Cypress Semiconductor CYS25G0101DX

CYS25G0101DX; rial-to-16-bit parallel conversion in re ceive path ■ Synchronous parallel int erface ❐ LVPECL compliant ❐ HSTL co mpliant ■ Internal transmit and recei ve phase-locked loops (PLLs) ■ Differ ential CML serial input ❐ 50 mV input sensitivity ❐ 100internal term ination and DC restoration ■ Differen tial CML serial output ❐ Source match ed for 50 transmission lines (100  dif.


Cypress Semiconductor CYS25G0101DX

ferential transmission lines) ■ Direct interface to standard fiber optic modu les ■ Less than 1.0W typical power 120-pin 14 mm × 14 mm TQFP ■ Stand by power saving mode for inactive loops ■ 0.25 BiCMOS technology ■ Pb-f ree packages available Functional Desc ription The CYS25G0101DX SONET OC-48 Tr ansceiver is a communications building block for high speed SONET data c.


Cypress Semiconductor CYS25G0101DX

ommunications. It provides complete para llel-to-serial and serial-to-parallel c onversion, clock generation, and clock and data recovery operations in a singl e chip optimized for full SONET complia nce. Transmit Path New data is accepted at the 16-bit parallel transmit interf ace at a rate of 155.52 MHz. This data is passed to a small integrated FIFO to enable flexible t.





Part

CYS25G0101DX

Description

SONET OC-48 Transceiver



Feature


CYS25G0101DX SONET OC-48 Transceiver SO NET OC-48 Transceiver Features ■ SONE T OC-48 operation ■ Bellcore and ITU jitter compliance ■ 2.488 GBaud seria l signaling rate ■ Multiple selectabl e loopback or loop through modes ■ Si ngle 155.52 MHz reference clock ■ Tra nsmit FIFO for flexible data interface clocking ■ 16-bit parallel-to-serial conversion in transmit path ■ Se.
Manufacture

Cypress Semiconductor

Datasheet
Download CYS25G0101DX Datasheet




 CYS25G0101DX
CYS25G0101DX
SONET OC-48 Transceiver
SONET OC-48 Transceiver
Features
SONET OC-48 operation
Bellcore and ITU jitter compliance
2.488 GBaud serial signaling rate
Multiple selectable loopback or loop through modes
Single 155.52 MHz reference clock
Transmit FIFO for flexible data interface clocking
16-bit parallel-to-serial conversion in transmit path
Serial-to-16-bit parallel conversion in receive path
Synchronous parallel interface
LVPECL compliant
HSTL compliant
Internal transmit and receive phase-locked loops (PLLs)
Differential CML serial input
50 mV input sensitivity
100internal termination and DC restoration
Differential CML serial output
Source matched for 50transmission lines (100 differential
transmission lines)
Direct interface to standard fiber optic modules
Less than 1.0W typical power
120-pin 14 mm × 14 mm TQFP
Standby power saving mode for inactive loops
0.25BiCMOS technology
Pb-free packages available
Functional Description
The CYS25G0101DX SONET OC-48 Transceiver is a
communications building block for high speed SONET data
communications. It provides complete parallel-to-serial and
serial-to-parallel conversion, clock generation, and clock and
data recovery operations in a single chip optimized for full
SONET compliance.
Transmit Path
New data is accepted at the 16-bit parallel transmit interface at
a rate of 155.52 MHz. This data is passed to a small integrated
FIFO to enable flexible transfer of data between the SONET
processor and the transmit serializer. As each 16-bit word is read
from the transmit FIFO, it is serialized and sent out to the high
speed differential line driver at a rate of 2.488 Gbits per second.
Receive Path
As serial data is received at the differential line receiver, it is
passed to a clock and data recovery (CDR) PLL that extracts a
precision low jitter clock from the transitions in the data stream.
This bit rate clock is used to sample the data stream and receive
the data. Every 16-bit times, a new word is presented at the
receive parallel interface along with a clock.
Parallel Interface
The parallel I/O interface supports high speed bus communica-
tions using HSTL signaling levels to minimize both power
consumption and board landscape. The HSTL outputs are
capable of driving unterminated transmission lines of less than
70 mm and terminated 50transmission lines of more than twice
that length.
The CYS25G0101DX Transceiver’s parallel HSTL I/O can also
be configured to operate at LVPECL signaling levels. This is
done externally by changing VDDQ, VREF and creating a simple
circuit at the termination of the transceiver’s parallel output
interface.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-02009 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 24, 2013




 CYS25G0101DX
CYS25G0101DX
Logic Block Diagram
(155.52 MHz)
TXCLKI TXD[15:0]
FIFO_RST
16
FIFO_ERR
TXCLKO
(155.52 MHz)
REFCLK
(155.52 MHz)
RXCLK
RXD[15:0]
16
LOOPTIME
Input
Register
TX PLL
X16
FIFO
16
Shifter
TX Bit-Clock
Output
Register
16
Shifter
Recovered
Bit-Clock
Lock-to-Ref
RX CDR
PLL
Retimed
Data
DIAGLOOP
LINELOOP
LOOPA
Lock-to-Data/
Clock Control
Logic
OUT
PWRDN LOCKREF SD LFI RESET IN
Document Number: 38-02009 Rev. *O
Page 2 of 22




 CYS25G0101DX
CYS25G0101DX
Contents
Clocking ............................................................................ 4
Pin Configuration ............................................................. 5
Pin Descriptions ............................................................... 6
CYS25G0101DX Operation .............................................. 8
CYS25G0101DX Transmit Data Path ............................... 8
Operating Modes ......................................................... 8
Phase Align Buffer ....................................................... 8
Transmit PLL Clock Multiplier ...................................... 8
Serializer ..................................................................... 8
Serial Output Driver ..................................................... 8
CYS25G0101DX Receive Data Path ................................ 8
Serial Line Receivers .................................................. 8
Lock to Data Control .................................................... 8
Clock Data Recovery ................................................... 8
External Filter .............................................................. 8
Deserializer ................................................................. 9
Loopback Timing Modes ............................................. 9
Reset Modes ............................................................... 9
Power Down Mode ...................................................... 9
LVPECL Compliance ................................................... 9
Maximum Ratings ........................................................... 10
Power Up Requirements ........................................... 10
Operating Range ............................................................. 10
DC Specifications ........................................................... 10
DC Specifications ........................................................... 10
DC Specifications ........................................................... 11
DC Specifications ........................................................... 11
DC Specifications ........................................................... 12
AC Test Loads and Waveforms ..................................... 12
AC Specifications ........................................................... 13
AC Specifications ........................................................... 13
AC Specifications ........................................................... 14
Jitter Specifications ....................................................... 14
Jitter Waveforms ............................................................ 15
Switching Waveforms .................................................... 16
Typical IO Terminations ................................................. 17
Ordering Information ...................................................... 19
Ordering Code Definitions ......................................... 19
Package Diagram ............................................................ 20
Document History Page ................................................. 21
Sales, Solutions, and Legal Information ...................... 22
Worldwide Sales and Design Support ....................... 22
Products .................................................................... 22
PSoC® Solutions ...................................................... 22
Cypress Developer Community ................................. 22
Technical Support ..................................................... 22
Document Number: 38-02009 Rev. *O
Page 3 of 22




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