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HEADER CONNECTOR. A3-xxxA-2xx Datasheet

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HEADER CONNECTOR. A3-xxxA-2xx Datasheet
















A3-xxxA-2xx CONNECTOR. Datasheet pdf. Equivalent













Part

A3-xxxA-2xx

Description

HEADER CONNECTOR



Feature


www.DataSheet4U.com 512MB, 1GB, 2GB Reg istered DIMM Preliminary DDR SDRAM DD R SDRAM Registered Module 184pin Regist ered Module based on 512Mb C-die with 7 2-bit ECC 66 TSOP-II and 60 ball FBGA with Pb-Free (RoHS compliant) DataShee t4U.com DataShee Revision 0.1 October . 2004 Rev. 0.1 October, 2004 DataShe et4U.com www.DataSheet4U.com 512MB, 1 GB, 2GB Registered.
Manufacture

Hirose Electric

Datasheet
Download A3-xxxA-2xx Datasheet


Hirose Electric A3-xxxA-2xx

A3-xxxA-2xx; DIMM Revision History Revision 0.0 (Sep tember, 2004) - First release Revision 0.1 (October, 2004) - Changed IDD curre nt. Preliminary DDR SDRAM et4U.com D ataSheet4U.com DataShee Rev. 0.1 Octo ber, 2004 DataSheet4U.com www.DataShe et4U.com 512MB, 1GB, 2GB Registered DI MM 184Pin Registered DIMM based on 512M b C-die (x4, x8) Ordering Information P art Number M312L65.


Hirose Electric A3-xxxA-2xx

23CUS-CB3/A2/B0 M312L2923CUS-CB3/A2/B0 M 312L2920CUS-CB3/A2/B0 M312L5628CU0-CA2/ B0 M312L6523CZ0-CCC/B3/A2/B0 M312L2923C Z0-CCC/B3/A2/B0 M312L2920CZ0-CCC/B3/A2/ B0 M312L5720CZ0-CCC/B3/A2/B0 Density 51 2MB 1GB 1GB 2GB 512MB 1GB 1GB 2GB Organ ization 64M x 72 128M x 72 128M x 72 25 6M x 72 64Mx72 128M x 72 128M x 72 256M x 72 Preliminary DDR SDRAM Component Composition 64Mx8.


Hirose Electric A3-xxxA-2xx

( K4H510838C) * 9EA 64Mx8( K4H510838C) * 18EA 128Mx4( K4H510438C) * 18EA st.256 Mx4( K4H1G0638C) * 18EA 64Mx8( K4H51083 8C) * 9EA 64Mx8( K4H510838C) * 18EA 128 Mx4( K4H510438C) * 18EA 128Mx4( K4H5104 38C) * 36EA Height 1,200mil 1,200mil 1 ,200mil 1,200mil 1,125mil 1,125mil 1,12 5mil 1,200mil Operating Frequencies CC (DDR400@CL=3) Speed @CL2 Speed @CL2.5 S peed @CL3 CL-tRCD-.





Part

A3-xxxA-2xx

Description

HEADER CONNECTOR



Feature


www.DataSheet4U.com 512MB, 1GB, 2GB Reg istered DIMM Preliminary DDR SDRAM DD R SDRAM Registered Module 184pin Regist ered Module based on 512Mb C-die with 7 2-bit ECC 66 TSOP-II and 60 ball FBGA with Pb-Free (RoHS compliant) DataShee t4U.com DataShee Revision 0.1 October . 2004 Rev. 0.1 October, 2004 DataShe et4U.com www.DataSheet4U.com 512MB, 1 GB, 2GB Registered.
Manufacture

Hirose Electric

Datasheet
Download A3-xxxA-2xx Datasheet




 A3-xxxA-2xx
www.DataSheet4U.com
512MB, 1GB, 2GB Registered DIMM
Preliminary
DDR SDRAM
DDR SDRAM Registered Module
184pin Registered Module based on 512Mb C-die
with 72-bit ECC
66 TSOP-II and 60 ball FBGA with Pb-Free
(RoHS compliant)
DataSheet4U.com
DataShee
Revision 0.1
October. 2004
DataSheet4U.com
Rev. 0.1 October, 2004




 A3-xxxA-2xx
www.DataSheet4U.com
512MB, 1GB, 2GB Registered DIMM
Revision History
Revision 0.0 (September, 2004)
- First release
Revision 0.1 (October, 2004)
- Changed IDD current.
Preliminary
DDR SDRAM
et4U.com
DataSheet4U.com
DataShee
DataSheet4U.com
Rev. 0.1 October, 2004




 A3-xxxA-2xx
www.DataSheet4U.com
512MB, 1GB, 2GB Registered DIMM
Preliminary
DDR SDRAM
184Pin Registered DIMM based on 512Mb C-die (x4, x8)
Ordering Information
Part Number
M312L6523CUS-CB3/A2/B0
M312L2923CUS-CB3/A2/B0
M312L2920CUS-CB3/A2/B0
M312L5628CU0-CA2/B0
M312L6523CZ0-CCC/B3/A2/B0
M312L2923CZ0-CCC/B3/A2/B0
M312L2920CZ0-CCC/B3/A2/B0
M312L5720CZ0-CCC/B3/A2/B0
Density
512MB
1GB
1GB
2GB
512MB
1GB
1GB
2GB
Organization
64M x 72
128M x 72
128M x 72
256M x 72
64Mx72
128M x 72
128M x 72
256M x 72
Component Composition
64Mx8( K4H510838C) * 9EA
64Mx8( K4H510838C) * 18EA
128Mx4( K4H510438C) * 18EA
st.256Mx4( K4H1G0638C) * 18EA
64Mx8( K4H510838C) * 9EA
64Mx8( K4H510838C) * 18EA
128Mx4( K4H510438C) * 18EA
128Mx4( K4H510438C) * 36EA
Height
1,200mil
1,200mil
1,200mil
1,200mil
1,125mil
1,125mil
1,125mil
1,200mil
Operating Frequencies
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
CC(DDR400@CL=3)
-
166MHz
200MHz
3-3-3
et4U.com
B3(DDR333@CL=2.5)
133MHz
166MHz
-
2.5-3-3
A2(DDR266@CL=2)
133MHz
133MHz
-
2-3-3
DataSheet4U.com
B0(DDR266@CL=2.5)
100MHz
133MHz
-
2.5-3-3
DataShee
Feature
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16)
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
• Programmable Burst length (2, 4, 8)
• Programmable Burst type (sequential & interleave)
• Edge aligned data output, center aligned data input
• Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh)
• Serial presence detect with EEPROM
• SSTL_2 Interface
• 66pin TSOP II and 60 ball FBGA Pb-Free package
RoHS compliant
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.1 October, 2004
DataSheet4U.com




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