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Data Recovery. ADN2814 Datasheet

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Data Recovery. ADN2814 Datasheet
















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Part

ADN2814

Description

Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery



Feature


Data Sheet Continuous Rate 10 Mb/s to 6 75 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2814 FEATU RES GENERAL DESCRIPTION Serial data i nput: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/ gene ration/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery archit ecture Loss-of-sign.
Manufacture

Analog Devices

Datasheet
Download ADN2814 Datasheet


Analog Devices ADN2814

ADN2814; al (LOS) detect range: 2.3 mV to 19 mV I ndependent slice level adjust and LOS d etector No reference clock required Los s-of-lock indicator I2C® interface to access optional features Single-supply operation: 3.3 V Low power: 435 mW typi cal 5 mm × 5 mm, 32-lead LFCSP, Pb fre e APPLICATIONS SONET OC-1/-3/-12 and al l associated FEC rates ESCON, Fast Ethe rnet, serial digital.


Analog Devices ADN2814

interfaces (DTV) WDM transponders Regen erators/repeaters Test equipment Broadb and cross-connects and routers The ADN 2814 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 10 Mb/s to 675 Mb/s. T he ADN2814 automatically locks to all d ata rates without the need for an exter nal reference cloc.


Analog Devices ADN2814

k or programming. All SONET jitter requi rements are met, including jitter trans fer, jitter generation, and jitter tole rance. All specifications are quoted fo r −40°C to +85°C ambient temperatur e, unless otherwise noted. This device, together with a PIN diode and a TIA pr eamplifier, can implement a highly inte grated, low cost, low power fiber optic receiver. The receive.





Part

ADN2814

Description

Continuous Rate 10 Mb/s to 675 Mb/s Clock and Data Recovery



Feature


Data Sheet Continuous Rate 10 Mb/s to 6 75 Mb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2814 FEATU RES GENERAL DESCRIPTION Serial data i nput: 10 Mb/s to 675 Mb/s Exceeds SONET requirements for jitter transfer/ gene ration/tolerance Quantizer sensitivity: 3.3 mV typical Adjustable slice level: ±95 mV Patented clock recovery archit ecture Loss-of-sign.
Manufacture

Analog Devices

Datasheet
Download ADN2814 Datasheet




 ADN2814
Data Sheet
Continuous Rate 10 Mb/s to 675 Mb/s Clock and
Data Recovery IC with Integrated Limiting Amp
ADN2814
FEATURES
GENERAL DESCRIPTION
Serial data input: 10 Mb/s to 675 Mb/s
Exceeds SONET requirements for jitter transfer/
generation/tolerance
Quantizer sensitivity: 3.3 mV typical
Adjustable slice level: ±95 mV
Patented clock recovery architecture
Loss-of-signal (LOS) detect range: 2.3 mV to 19 mV
Independent slice level adjust and LOS detector
No reference clock required
Loss-of-lock indicator
I2C® interface to access optional features
Single-supply operation: 3.3 V
Low power: 435 mW typical
5 mm × 5 mm, 32-lead LFCSP, Pb free
APPLICATIONS
SONET OC-1/-3/-12 and all associated FEC rates
ESCON, Fast Ethernet, serial digital interfaces (DTV)
WDM transponders
Regenerators/repeaters
Test equipment
Broadband cross-connects and routers
The ADN2814 provides the receiver functions of quantization,
signal level detect, and clock and data recovery for continuous
data rates from 10 Mb/s to 675 Mb/s. The ADN2814 automati-
cally locks to all data rates without the need for an external
reference clock or programming. All SONET jitter requirements
are met, including jitter transfer, jitter generation, and jitter
tolerance. All specifications are quoted for −40°C to +85°C
ambient temperature, unless otherwise noted.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power fiber
optic receiver.
The receiver front-end, loss-of-signal (LOS) detector circuit
indicates when the input signal level has fallen below a user-
adjustable threshold. The LOS detect circuit has hysteresis to
prevent chatter at the output.
The ADN2814 is available in a compact 5 mm × 5 mm,
32-lead LFCSP.
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2 VCC VEE
SLICEP/SLICEN
PIN
NIN
2
QUANTIZER
FREQUENCY
DETECT
LOOP
FILTER
PHASE
SHIFTER
PHASE
DETECT
LOOP
FILTER
VCO
VREF
LOS
DETECT
DATA
RE-TIMING
2
2
THRADJ
LOS
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
Figure 1.
ADN2814
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 © 2005–2012 Analog Devices, Inc. All rights reserved.




 ADN2814
ADN2814
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
Jitter Specifications....................................................................... 4 
Output and Timing Specifications ............................................. 5 
Absolute Maximum Ratings............................................................ 6 
Thermal Characteristics .............................................................. 6 
ESD Caution.................................................................................. 6 
Timing Characteristics..................................................................... 7 
Pin Configuration and Function Descriptions............................. 8 
Typical Performance Characteristics ............................................. 9 
I2C Interface Timing and Internal Register Description........... 10 
Terminology .................................................................................... 12 
Jitter Specifications ......................................................................... 13 
Theory of Operation ...................................................................... 14 
REVISION HISTORY
3/12—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
5/10—Rev. A to Rev. B
Changes to Figure 5 and Table 5..................................................... 8
Changes to Figure 24...................................................................... 21
Added Exposed Pad Notation to Outline Dimensions ............. 26
3/09—Rev. 0 to Rev. A
Updated Outline Dimensions ....................................................... 26
Changes to Ordering Guide .......................................................... 26
9/05—Revision 0: Initial Version
Data Sheet
Functional Description.................................................................. 16 
Frequency Acquisition............................................................... 16 
Limiting Amplifier ..................................................................... 16 
Slice Adjust.................................................................................. 16 
Loss-of-Signal (LOS) Detector ................................................. 16 
Lock Detector Operation .......................................................... 17 
Harmonic Detector .................................................................... 17 
SQUELCH Mode........................................................................ 18 
I2C Interface ................................................................................ 18 
Reference Clock (Optional) ...................................................... 18 
Applications Information .............................................................. 21 
PCB Design Guidelines ............................................................. 21 
DC-Coupled Application .......................................................... 23 
Coarse Data Rate Readback Look-Up Table............................... 24 
Outline Dimensions ....................................................................... 26 
Ordering Guide .......................................................................... 26 
Rev. C | Page 2 of 28




 ADN2814
Data Sheet
ADN2814
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
Differential Input Sensitivity
Input Offset
Input RMS Noise
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
QUANTIZER—SLICE ADJUSTMENT
Gain
Differential Control Voltage Input
Control Voltage Range
Slice Threshold Offset
LOSS-OF-SIGNAL (LOS) DETECT
Loss-of-Signal Detect Range (see Figure 6)
Hysteresis (Electrical)
LOS Assert Time
LOS Deassert Time
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
ACQUISITION TIME
Lock to Data Mode
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Coarse Readback
Fine Readback
Conditions
@ PIN or NIN, dc-coupled
PIN − NIN
DC-coupled (see Figure 27, Figure 28, and Figure 29)
223 − 1 PRBS, ac-coupled,1 BER = 1 × 10–10
BER = 1 × 10–10
@ 2.5 GHz
Differential
SLICEP − SLICEN = ±0.5 V
SLICEP − SLICEN
DC level @ SLICEP or SLICEN
RTHRESH = 0 Ω
RTHRESH = 100 kΩ
OC-12
RTHRESH = 0 Ω
RTHRESH = 100 kΩ
OC-1
RTHRESH = 0 Ω
RTHRESH = 10 kΩ
DC-coupled 2
DC-coupled2
With respect to nominal
With respect to nominal
10 Mb/s
OC-12
OC-12
OC-3
OC-1
10 Mb/s
See Table 13
In addition to REFCLK accuracy
Data rate ≤ 20 Mb/s
Data rate > 20 Mb/s
Min Typ Max Unit
1.8 2.8 V
2.0 V
2.3 2.5 2.8 V
6 3.3
mV p-p
500 μV
290 μV rms
10 675 Mb/s
−15 dB
100 Ω
0.65 pF
0.10
−0.95
VEE
0.11
1
0.13
+0.95
0.95
V/V
V
V
mV
14 16.5 19 mV
2.3 3.5 4.7 mV
6.4 7.2 8.0 dB
4.6 6.2 7.8 dB
5.5 6.6 7.7 dB
3.1 5.4 7.7 dB
500 ns
400 ns
1000
250
5
200
ppm
ppm
ms
μs
2.0 ms
3.4 ms
9.8 ms
40.0 ms
20.0 ms
10 %
200 ppm
100 ppm
Rev. C | Page 3 of 28




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