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level FET. BUK7L06-34ARC Datasheet

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level FET. BUK7L06-34ARC Datasheet
















BUK7L06-34ARC FET. Datasheet pdf. Equivalent













Part

BUK7L06-34ARC

Description

TrenchPLUS standard level FET



Feature


www.DataSheet4U.com BUK7L06-34ARC Trenc hPLUS standard level FET Rev. 03 — 3 December 2003 Product data 1. Product profile 1.1 Description N-channel enha ncement mode field-effect power transi stor in a plastic package using TrenchM OS™ technology, featuring very low on -state resistance, integral gate resist or, ESD protection diodes and clamping diodes that are guaranteed.
Manufacture

NXP

Datasheet
Download BUK7L06-34ARC Datasheet


NXP BUK7L06-34ARC

BUK7L06-34ARC; to prevent the MOSFET avalanching. 1.2 Features s ESD and overvoltage protect ion s Internal gate resistor s Q101 com pliant s On-state resistance 5.1 mΩ ( typ). 1.3 Applications s 12 V loads s Motors, lamps and solenoids. 1.4 Quick reference data s VDSR(CL) = 41 V (typ) s ID ≤ 147 A s RDSon = 5.1 mΩ (typ ) s Ptot ≤ 250 W. 2. Pinning informa tion Table 1: Pin 1 2 3 mb.


NXP BUK7L06-34ARC

Pinning - SOT78C, simplified outline a nd symbol Simplified outline mb Descr iption gate (g) drain (d) source (s) mo unting base, connected to drain (d) Sy mbol d g s MBL521 1 2 3 MBL370 SO T78C (TO-220) DataSheet 4 U .com www. DataSheet4U.com Philips Semiconductors BUK7L06-34ARC TrenchPLUS standard lev el FET 3. Ordering information Table 2 : Ordering information.


NXP BUK7L06-34ARC

Package Name BUK7L06-34ARC TO-220 Descr iption Version Plastic single-ended pac kage; heatsink mounted; 1 mounting hole ; 3 leads. SOT78C Type number 4. Limit ing values Table 3: Limiting values In accordance with the Absolute Maximum Ra ting System (IEC 60134). Symbol VDS VDG R VGS ID Parameter drain-source voltage (DC) drain-gate voltage (DC) gate-sour ce voltage (DC) dr.




Part

BUK7L06-34ARC

Description

TrenchPLUS standard level FET



Feature


www.DataSheet4U.com BUK7L06-34ARC Trenc hPLUS standard level FET Rev. 03 — 3 December 2003 Product data 1. Product profile 1.1 Description N-channel enha ncement mode field-effect power transi stor in a plastic package using TrenchM OS™ technology, featuring very low on -state resistance, integral gate resist or, ESD protection diodes and clamping diodes that are guaranteed.
Manufacture

NXP

Datasheet
Download BUK7L06-34ARC Datasheet




 BUK7L06-34ARC
www.DataSheet4U.com
BUK7L06-34ARC
TrenchPLUS standard level FET
Rev. 03 — 3 December 2003
Product data
1. Product profile
1.1 Description
N-channel enhancement mode field-effect power transistor in a plastic package using
TrenchMOS™ technology, featuring very low on-state resistance, integral gate
resistor, ESD protection diodes and clamping diodes that are guaranteed to prevent
the MOSFET avalanching.
1.2 Features
s ESD and overvoltage protection
s Internal gate resistor
s Q101 compliant
s On-state resistance 5.1 m(typ).
1.3 Applications
s 12 V loads
s Motors, lamps and solenoids.
1.4 Quick reference data
s VDSR(CL) = 41 V (typ)
s ID 147 A
s RDSon = 5.1 m(typ)
s Ptot 250 W.
2. Pinning information
Table 1: Pinning - SOT78C, simplified outline and symbol
Pin Description
Simplified outline
1 gate (g)
2 drain (d)
mb
3 source (s)
mb mounting base,
connected to drain (d)
123
MBL370
SOT78C (TO-220)
Symbol
g
d
s MBL521
DataSheet4 U .com




 BUK7L06-34ARC
www.DataSheet4U.com
Philips Semiconductors
BUK7L06-34ARC
TrenchPLUS standard level FET
3. Ordering information
Table 2: Ordering information
Type number
Package
Name
Description
Version
BUK7L06-34ARC TO-220
Plastic single-ended package; heatsink mounted; 1 mounting hole; 3 leads. SOT78C
4. Limiting values
Table 3: Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
VDS
VDGR
VGS
ID
drain-source voltage (DC)
drain-gate voltage (DC)
gate-source voltage (DC)
drain current (DC)
RGS = 20 k
Tmb = 25 °C; VGS = 10 V;
Figure 2 and 3
IDM
Ptot
IDG(CL)
IGS(CL)
peak drain current
total power dissipation
drain-gate clamping current
gate-source clamping current
Tstg storage temperature
Tj junction temperature
Source-drain diode
IDR reverse drain current (DC)
Tmb = 100 °C; VGS = 10 V; Figure 2
Tmb = 25 °C; pulsed; tp 10 µs;
Figure 3
Tmb = 25 °C; Figure 1
tp = 5 ms; δ = 0.01
continuous
tp = 5 ms; δ = 0.01
Tmb = 25 °C
IDRM
peak reverse drain current
Tmb = 25 °C; pulsed; tp 10 µs
Avalanche ruggedness
EDS(CL)S
non-repetitive drain-source clamped clamped inductive load; ID = 75 A;
energy
VDS 34 V; VGS = 10 V; starting
Tj = 25 °C
Electrostatic discharge
Vesd electrostatic discharge voltage; all human body model; C = 100 pF;
pins R = 1.5 k
human body model; C = 250 pF;
R = 1.5 k
Min
[1] -
[1] -
[1] -
[2] -
[3] -
[2] -
-
-
-
-
-
55
55
[2] -
[3] -
-
-
-
-
[1] Voltage is limited by clamping.
[2] Current is limited by power dissipation chip rating.
[3] Continuous current is limited by package.
Max Unit
34 V
34 V
±20 V
147 A
75 A
103 A
590 A
250
50
10
50
+175
+175
W
mA
mA
mA
°C
°C
147 A
75 A
590 A
1.0 J
8 kV
8 kV
9397 750 12162
Product data
DataSheet4 U .com
Rev. 03 — 3 December 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
2 of 14




 BUK7L06-34ARC
www.DataSheet4U.com
Philips Semiconductors
BUK7L06-34ARC
TrenchPLUS standard level FET
120
Pder
(%)
80
40
03na19
150
ID
(A)
100
Capped at 75 A due to package
50
03nj41
0
0 50 100 150 200
Tmb (°C)
Pder
=
-------P----t--o---t-------
P
×
100%
t o t ( 25 °C )
Fig 1. Normalized total power dissipation as a
function of mounting base temperature.
0
0 50
VGS 10 V
100 150 200
Tmb (°C)
Fig 2. Continuous drain current as a function of
mounting base temperature.
103
ID
(A)
102
10
Limit RDSon = VDS / ID
Capped at 75 A due to package
DC
03nj39
tp = 10 µs
100 µs
1 ms
10 ms
100 ms
1
10-1
1
10
VDS (V)
102
Tmb = 25 °C; IDM single pulse.
Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage.
9397 750 12162
Product data
DataSheet4 U .com
Rev. 03 — 3 December 2003
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
3 of 14




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