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D/A Converter. AD9755 Datasheet

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D/A Converter. AD9755 Datasheet






AD9755 Converter. Datasheet pdf. Equivalent




AD9755 Converter. Datasheet pdf. Equivalent





Part

AD9755

Description

14-Bit/ 300 MSPS High-Speed TxDAC+ D/A Converter



Feature


a 14-Bit, 300 MSPS High Speed TxDAC+® D/A Converter AD9755 FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Upd ate Rate Excellent SFDR and IMD Perform ance SFDR to Nyquist @ 25 MHz Output: 7 1 dB Internal Clock Doubling PLL Differ ential or Single-Ended Clock Input On-C hip 1.2 V Reference Single 3.3 V Supply Operation Power Dissipation: 155 mW @ 3.3 V 48-Lead LQFP .
Manufacture

Analog Devices

Datasheet
Download AD9755 Datasheet


Analog Devices AD9755

AD9755; APPLICATIONS Communications: LMDS, LMCS, MMDS Base Stations Digital Synthesis Q AM and OFDM PRODUCT DESCRIPTION The AD9 755 is a dual, muxed port, ultrahigh sp eed, singlechannel, 14-bit CMOS DAC. It integrates a high quality 14-bit TxDAC + core, a voltage reference, and digita l interface circuitry into a small 48-l ead LQFP package. The AD9755 offers exc eptional ac and dc.


Analog Devices AD9755

performance while supporting update rat es up to 300 MSPS. The AD9755 has been optimized for ultrahigh speed applicati ons up to 300 MSPS where data rates exc eed those possible on a single data int erface port DAC. The digital interface consists of two buffered .


Analog Devices AD9755

.

Part

AD9755

Description

14-Bit/ 300 MSPS High-Speed TxDAC+ D/A Converter



Feature


a 14-Bit, 300 MSPS High Speed TxDAC+® D/A Converter AD9755 FEATURES 14-Bit Dual Muxed Port DAC 300 MSPS Output Upd ate Rate Excellent SFDR and IMD Perform ance SFDR to Nyquist @ 25 MHz Output: 7 1 dB Internal Clock Doubling PLL Differ ential or Single-Ended Clock Input On-C hip 1.2 V Reference Single 3.3 V Supply Operation Power Dissipation: 155 mW @ 3.3 V 48-Lead LQFP .
Manufacture

Analog Devices

Datasheet
Download AD9755 Datasheet




 AD9755
a
14-Bit, 300 MSPS
High Speed TxDAC+® D/A Converter
AD9755
FEATURES
14-Bit Dual Muxed Port DAC
300 MSPS Output Update Rate
Excellent SFDR and IMD Performance
SFDR to Nyquist @ 25 MHz Output: 71 dB
Internal Clock Doubling PLL
Differential or Single-Ended Clock Input
On-Chip 1.2 V Reference
Single 3.3 V Supply Operation
Power Dissipation: 155 mW @ 3.3 V
48-Lead LQFP
APPLICATIONS
Communications: LMDS, LMCS, MMDS
Base Stations
Digital Synthesis
QAM and OFDM
PRODUCT DESCRIPTION
The AD9755 is a dual, muxed port, ultrahigh speed, single-
channel, 14-bit CMOS DAC. It integrates a high quality 14-bit
TxDAC+ core, a voltage reference, and digital interface circuitry
into a small 48-lead LQFP package. The AD9755 offers excep-
tional ac and dc performance while supporting update rates up
to 300 MSPS.
The AD9755 has been optimized for ultrahigh speed applica-
tions up to 300 MSPS where data rates exceed those possible on
a single data interface port DAC. The digital interface consists
of two buffered latches as well as control logic. These latches
can be time multiplexed to the high speed DAC in several ways.
This PLL drives the DAC latch at twice the speed of the exter-
nally applied clock and is able to interleave the data from the
two input channels. The resulting output data rate is twice that
of the two input channels. With the PLL disabled, an external
2× clock may be supplied and divided by two internally.
The CLK inputs (CLK+/CLK–) can be driven either differentially
or single-ended, with a signal swing as low as 1 V p-p.
FUNCTIONAL BLOCK DIAGRAM
DVDD DCOM
AVDD ACOM
PORT1
LATCH
PORT2
LATCH
MUX
DAC
IOUTA
IOUTB
CLK+
CLK–
CLKVDD
PLLVDD
CLKCOM
PLL
CLOCK
MULTIPLIER
REFERENCE
AD9755
RESET LPF DIV0 DIV1 PLLLOCK
REFIO
FSADJ
The DAC utilizes a segmented current source architecture com-
bined with a proprietary switching technique to reduce glitch
energy and maximize dynamic accuracy. Differential current
outputs support single-ended or differential applications. The
differential outputs each provide a nominal full-scale current
from 2 mA to 20 mA.
The AD9755 is manufactured on an advanced low cost 0.35 µm
CMOS process. It operates from a single supply of 3.0 V to 3.6 V
and consumes 155 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9755 is a member of a pin compatible family of high
speed TxDAC+s providing 10-, 12-, and 14-bit resolution.
2. Ultrahigh Speed 300 MSPS Conversion Rate.
3. Dual 14-Bit Latched, Multiplexed Input Ports. The AD9755
features a flexible digital interface allowing high speed data
conversion through either a single or dual port input.
4. Low Power. Complete CMOS DAC function operates on
155 mW from a 3.0 V to 3.6 V single supply. The DAC full-
scale current can be reduced for lower power operation.
5. On-Chip Voltage Reference. The AD9755 includes a 1.20 V
temperature compensated band gap voltage reference.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.




 AD9755
AD9755* Product Page Quick Links
Last Content Update: 11/01/2016
Comparable Parts
View a parametric search of comparable parts
Evaluation Kits
• AD9755 Evaluation Board
Documentation
Application Notes
• AN-137: A Digitally Programmable Gain and Attenuation
Amplifier Design
• AN-237: Choosing DACs for Direct Digital Synthesis
• AN-320A: CMOS Multiplying DACs and Op Amps
Combine to Build Programmable Gain Amplifier, Part 1
• AN-595: Understanding Pin Compatibility in the TxDAC®
Line of High Speed D/A Converters
• AN-642: Coupling a Single-Ended Clock Source to the
Differential Clock Input of Third-Generation TxDAC® and
TxDAC+® Products
• AN-912: Driving a Center-Tapped Transformer with a
Balanced Current-Output DAC
Data Sheet
• AD9755: 14-Bit, 300 MSPS High-Speed TxDAC+® D/A
Converter Data Sheet
Tools and Simulations
• AD9755 IBIS Models
Reference Materials
Informational
• Advantiv™ Advanced TV Solutions
Solutions Bulletins & Brochures
• Digital to Analog Converters ICs Solutions Bulletin
Design Resources
• AD9755 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9755 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
Submit a technical question or find your regional support
number
* This page was dynamically generated by Analog Devices, Inc. and inserted into this data sheet. Note: Dynamic changes to
the content on this page does not constitute a change to the revision number of the product data sheet. This content may be
frequently modified.




 AD9755
AD9755–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, CLKVDD = 3.3 V, IOUTFS = 20 mA, unless
otherwise noted.)
Parameter
Min
RESOLUTION
14
DC ACCURACY1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
–5
–3
ANALOG OUTPUT
Offset Error
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
–0.025
–2
–2
2.0
–1.0
REFERENCE OUTPUT
Reference Voltage
Reference Output Current3
1.14
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance
0.1
TEMPERATURE COEFFICIENTS
Offset Drift
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
Reference Voltage Drift
POWER SUPPLY
Supply Voltages
AVDD
DVDD
PLLVDD
CLKVDD
Analog Supply Current (IAVDD)4
Digital Supply Current (IDVDD)4
PLL Supply Current (IPLLVDD)4
Clock Supply Current (ICLKVDD)4
Power Dissipation4 (3 V, IOUTFS = 20 mA)
Power Dissipation5 (3 V, IOUTFS = 20 mA)
Power Supply Rejection Ratio6—AVDD
Power Supply Rejection Ratio6—DVDD
3.0
3.0
3.0
3.0
–1
–0.04
OPERATING RANGE
–40
NOTES
1Measured at IOUTA, driving a virtual ground.
2Nominal full-scale current, IOUTFS, is 32× the IREF current.
3An external buffer amplifier is recommended to drive any external load.
4100 MSPS fDAC with PLL on, fOUT = 100 MHz, all supplies = 3.0 V.
5300 MSPS fDAC.
6± 5% power supply variation.
Specifications subject to change without notice.
Typ
± 2.5
± 1.5
± 0.01
± 0.5
± 0.25
100
5
1.20
100
1
0
± 50
± 100
± 50
3.3
3.3
3.3
3.3
33
3.5
4.5
10.0
155
216
Max
+5
+3
+0.025
+2
+2
20.0
+1.25
1.26
1.25
3.6
3.6
3.6
3.6
36
4.5
5.1
11.5
165
+1
+0.04
+85
Unit
Bits
LSB
LSB
% of FSR
% of FSR
% of FSR
mA
V
k
pF
V
nA
V
M
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
V
V
V
V
mA
mA
mA
mA
mW
mW
% of FSR/V
% of FSR/V
°C
–2– REV. B



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