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Embedded Processor. ADSP-TS101S Datasheet

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Embedded Processor. ADSP-TS101S Datasheet






ADSP-TS101S Processor. Datasheet pdf. Equivalent




ADSP-TS101S Processor. Datasheet pdf. Equivalent





Part

ADSP-TS101S

Description

TigerSHARC Embedded Processor



Feature


www.DataSheet4U.com a KEY FEATURES 300 MHz, 3.3 ns Instruction Cycle Rate 6M B its of Internal—On-Chip—SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Comp utation Blocks—Each Containing an ALU , a Multiplier, a Shifter, and a Regist er File Dual Integer ALUs, Providing Da ta Addressing and Pointer Manipulation Integrated I/O Includes 14.
Manufacture

Analog Devices

Datasheet
Download ADSP-TS101S Datasheet


Analog Devices ADSP-TS101S

ADSP-TS101S; Channel DMA Controller, External Port, Four Link Ports, SDRAM Controller, Prog rammable Flag Pins, Two Timers, and Tim er Expired Pin for System Integration 1 149.1 IEEE Compliant JTAG Test Access P ort for On-Chip Emulation On-Chip Arbit ration for Glueless Multiprocessing wit h up to Eight TigerSHARC Processors on a Bus Embedded Processor ADSP-TS101S K EY BENEFITS Provid.


Analog Devices ADSP-TS101S

es High Performance Static Superscalar D SP Operations, Optimized for Telecommun ications Infrastructure and Other Large , Demanding Multiprocessor DSP Applicat ions Performs Exceptionally Well on DSP Algorithm and I/O Benchmarks (See Benc hmarks in Table 1 and Table 2) Supports Low Overhead DMA Transfers Between Int ernal Memory, External Memory, Memory-M apped Peripherals,.


Analog Devices ADSP-TS101S

Link Ports, Host Processors, and Other (Multiprocessor) DSPs Eases DSP Program ming Through Extremely Flexible Instruc tion Set and High Level Language Friend ly DSP Architecture Enables Scalable Mu ltiprocessing Systems with Low Communic ations Overhead T FUNCTIONAL BLOCK DI AGRAM COMPUTATIONAL BLOCKS SHIFTER PR OGRAM SEQUENCER PC BTB IRQ DATA ADDRES S GENERATION INTEG.

Part

ADSP-TS101S

Description

TigerSHARC Embedded Processor



Feature


www.DataSheet4U.com a KEY FEATURES 300 MHz, 3.3 ns Instruction Cycle Rate 6M B its of Internal—On-Chip—SRAM Memory 19 mm ؋ 19 mm (484-Ball) or 27 mm ؋ 27 mm (625-Ball) PBGA Package Dual Comp utation Blocks—Each Containing an ALU , a Multiplier, a Shifter, and a Regist er File Dual Integer ALUs, Providing Da ta Addressing and Pointer Manipulation Integrated I/O Includes 14.
Manufacture

Analog Devices

Datasheet
Download ADSP-TS101S Datasheet




 ADSP-TS101S
FEATURES
300 MHz, 3.3 ns instruction cycle rate
6M bits of internal—on-chip—SRAM memory
19 mm × 19 mm (484-ball) or 27 mm × 27 mm
(625-ball) PBGA package
Dual computation blocks—each containing an ALU, a multi-
plier, a shifter, and a register file
Dual integer ALUs, providing data addressing and pointer
manipulation
Integrated I/O includes 14-channel DMA controller, external
port, 4 link ports, SDRAM controller, programmable flag
pins, 2 timers, and timer expired pin for system integration
1149.1 IEEE compliant JTAG test access port for on-chip
emulation
On-chip arbitration for glueless multiprocessing with up to
8 TigerSHARC processors on a bus
TigerSHARC
Embedded Processor
ADSP-TS101S
BENEFITS
Provides high performance Static Superscalar DSP opera-
tions, optimized for telecommunications infrastructure
and other large, demanding multiprocessor DSP
applications
Performs exceptionally well on DSP algorithm and I/O bench-
marks (see benchmarks in Table 1 and Table 2)
Supports low overhead DMA transfers between internal
memory, external memory, memory-mapped peripherals,
link ports, other DSPs (multiprocessor), and host
processors
Eases DSP programming through extremely flexible instruc-
tion set and high-level language-friendly DSP architecture
Enables scalable multiprocessing systems with low commu-
nications overhead
COMPUTATIONAL BLOCKS
SHIFTER
ALU
MULTIPLIER
X
REGISTER
FILE
32 × 32
128 128
DAB
DAB
128 128
Y
REGISTER
FILE
32 × 32
MULTIPLIER
ALU
SHIFTER
PROGRAM SEQUENCER
PC BTB IRQ
ADDR
IAB FETCH
DATA ADDRESS GENERATION
INTEGER 32
J ALU
32 × 32
32 INTEGER
K ALU
32 × 32
32
128
32
128
32
128
I/O PROCESSOR
DMA
CONTROLLER
CONTROL/
STATUS/
TCBs
DMA ADDRESS
DMA DATA
INTERNAL MEMORY
MEMORY MEMORY MEMORY
M0 M1 M2
64K × 32 64K × 32 64K × 32
A DA DA D
6
JTAG PORT
SDRAM CONTROLLER
32 256
M0 ADDR
M0 DATA
M1 ADDR
M1 DATA
EXTERNAL PORT
MULTIPROCESSOR
INTERFACE
HOST INTERFACE
INPUT FIFO
32
ADDR
64
OUTPUT BUFFER
DATA
M2 ADDR
M2 DATA
I/O ADDRESS 32
OUTPUT FIFO
CLUSTER BUS
ARBITER
CNTRL
3
LINK PORT
CONTROLLER
L0 8
3
256 LINK DATA
L1
LINK
PORTS
8
3
CONTROL/
STATUS/
BUFFERS
L2 8
3
L3 8
Figure 1. Functional Block Diagram
TigerSHARC and the TigerSHARC logo are registered trademarks of Analog Devices, Inc.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2009 Analog Devices, Inc. All rights reserved.




 ADSP-TS101S
ADSP-TS101S
TABLE OF CONTENTS
Features ................................................................. 1
Benefits ................................................................. 1
Table of Contents ..................................................... 2
Revision History ...................................................... 2
General Description ................................................. 3
Dual Compute Blocks ............................................ 4
Data Alignment Buffer (DAB) .................................. 4
Dual Integer ALUs (IALUs) .................................... 4
Program Sequencer ............................................... 5
On-Chip SRAM Memory ........................................ 5
External Port
(Off-Chip Memory/Peripherals Interface) ................ 6
DMA Controller ................................................... 7
Link Ports ........................................................... 9
Timer and General-Purpose I/O ............................... 9
Reset and Booting ................................................. 9
Low Power Operation ............................................ 9
Clock Domains .................................................... 9
Output Pin Drive Strength Control ......................... 10
Power Supplies ................................................... 10
Filtering Reference Voltage and Clocks .................... 10
Development Tools ............................................. 10
REVISION HISTORY
5/09—Rev. B to Rev. C
Added parameter value (IDD_A max) in
Operating Conditions ............................................. 20
Updated footnotes in 484-Ball PBGA (B-484) ............... 43
Updated footnotes in 625-Ball PBGA (B-625) ............... 44
Added surface-mount design info
in Surface-Mount Design ......................................... 44
Updated models in Ordering Guide ............................ 45
Designing an Emulator-Compatible
DSP Board (Target) .......................................... 11
Additional Information ........................................ 11
Pin Function Descriptions ........................................ 12
Pin States at Reset ................................................ 12
Pin Definitions ................................................... 12
Strap Pin Function Descriptions ................................ 19
Specifications ........................................................ 20
Operating Conditions ........................................... 20
Electrical Characteristics ....................................... 20
Absolute Maximum Ratings ................................... 21
ESD Caution ...................................................... 21
Package Information ............................................ 21
Timing Specifications ........................................... 21
Output Drive Currents ......................................... 32
Test Conditions .................................................. 34
Environmental Conditions .................................... 36
PBGA Pin Configurations ........................................ 37
Outline Dimensions ................................................ 43
Surface-Mount Design ............................................. 44
Ordering Guide ..................................................... 45
Rev. C | Page 2 of 48 | May 2009




 ADSP-TS101S
ADSP-TS101S
GENERAL DESCRIPTION
The ADSP-TS101S TigerSHARC® processor is an ultrahigh per-
formance, Static SuperscalarTM processor optimized for large
signal processing tasks and communications infrastructure. The
DSP combines very wide memory widths with dual computa-
tion blocks—supporting 32- and 40-bit floating-point and 8-,
16-, 32-, and 64-bit fixed-point processing—to set a new stan-
dard of performance for digital signal processors. The
TigerSHARC processor’s Static Superscalar architecture lets the
processor execute up to four instructions each cycle, performing
24 fixed-point (16-bit) operations or six floating-point
operations.
Three independent 128-bit-wide internal data buses, each
connecting to one of the three 2M bit memory banks, enable
quad word data, instruction, and I/O accesses and provide
14.4G bytes per second of internal memory bandwidth. Operat-
ing at 300 MHz, the ADSP-TS101S processor’s core has a 3.3 ns
instruction cycle time. Using its single-instruction, multiple-
data (SIMD) features, the ADSP-TS101S can perform 2.4 billion
40-bit MACs or 600 million 80-bit MACs per second. Table 1
and Table 2 show the DSP’s performance benchmarks.
Table 1. General-Purpose Algorithm Benchmarks
at 300 MHz
Benchmark
Speed
Clock
Cycles
32-bit algorithm, 600 million MACs/s peak performance
1024 point complex FFT (Radix 2) 32.78 μs
9,835
50-tap FIR on 1024 input
91.67 μs
27,500
Single FIR MAC
1.83 ns
0.55
16-bit algorithm, 2.4 billion MACs/s peak performance
256 point complex FFT (Radix 2)
3.67 μs
1,100
50-tap FIR on 1024 input
24.0 μs
7,200
Single FIR MAC
0.47 ns
0.14
Single complex FIR MAC
1.9 ns
0.57
I/O DMA transfer rate
External port
800M bytes/s n/a
Link ports (each)
250M bytes/s n/a
Table 2. 3G Wireless Algorithm Benchmarks
Benchmark
Turbo decode
384 kbps data channel
Viterbi decode
12.2 kbps AMR3 voice channel
Complex correlation
3.84 Mcps4 with a spreading factor of 256
1 The execution speed is in instruction cycles per second.
Execution
(MIPS)1
51 MIPS2
0.86 MIPS
0.27 MIPS
2 This value is for six iterations of the algorithm. For eight iterations of the turbo
decoder, this benchmark is 67 MIPS.
3 Adaptive multi rate (AMR)
4 Megachips per second (Mcps)
The ADSP-TS101S is code compatible with the other
TigerSHARC processors.
The Functional Block Diagram on Page 1 shows the processor’s
architectural blocks. These blocks include:
• Dual compute blocks, each consisting of an ALU, multi-
plier, 64-bit shifter, and 32-word register file and associated
data alignment buffers (DABs)
• Dual integer ALUs (IALUs), each with its own 31-word
register file for data addressing
• A program sequencer with instruction alignment buffer
(IAB), branch target buffer (BTB), and interrupt controller
• Three 128-bit internal data buses, each connecting to one
of three 2M bit memory banks
• On-chip SRAM (6M bit)
• An external port that provides the interface to host proces-
sors, multiprocessing space (DSPs), off-chip memory-
mapped peripherals, and external SRAM and SDRAM
• A 14-channel DMA controller
• Four link ports
• Two 64-bit interval timers and timer expired pin
• A 1149.1 IEEE compliant JTAG test access port for on-chip
emulation
Figure 2 shows a typical single-processor system with external
SDRAM. Figure 4 on Page 8 shows a typical multiprocessor
system.
The TigerSHARC processor uses a Static Superscalar architec-
ture. This architecture is superscalar in that the ADSP-TS101S
processor’s core can execute simultaneously from one to four
32-bit instructions encoded in a very large instruction word
(VLIW) instruction line using the DSP’s dual compute blocks.
Because the DSP does not perform instruction reordering at
runtime—the programmer selects which operations will execute
in parallel prior to runtime—the order of instructions is static.
With few exceptions, an instruction line, whether it contains
one, two, three, or four 32-bit instructions, executes with a
throughput of one cycle in an eight-deep processor pipeline.
For optimal DSP program execution, programmers must follow
the DSP’s set of instruction parallelism rules when encoding an
instruction line. In general, the selection of instructions that the
DSP can execute in parallel each cycle depends on the instruc-
tion line resources each instruction requires and on the source
and destination registers used in the instructions. The program-
mer has direct control of three core components—the IALUs,
the compute blocks, and the program sequencer.
Static Superscalar is a trademark of Analog Devices, Inc.
Rev. C | Page 3 of 48 | May 2009



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