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Signal Controllers. 56F8036 Datasheet

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Signal Controllers. 56F8036 Datasheet
















56F8036 Controllers. Datasheet pdf. Equivalent













Part

56F8036

Description

16-bit Digital Signal Controllers



Feature


www.DataSheet4U.com 56F8036 Data Sheet Preliminary Technical Data 56F8000 16- bit Digital Signal Controllers MC56F80 36 Rev. 3 01/2007 freescale.com Docum ent Revision History Version History Re v. 0 Rev. 1 Initial public release. • In Table 10-4, added an entry for flas h data retention with less than 100 pro gram/erase cycles (minimum 20 years). In Table 10-6, chan.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F8036 Datasheet


Freescale Semiconductor 56F8036

56F8036; ged the device clock speed in STOP mode from 8MHz to 4MHz. • In Table 10-12, changed the typical relaxation oscillat or output frequency in Standby mode fro m 400kHz to 200kHz. • Changed input p ropagation delay values in Table 10-21 as follows: Old values: 1 μs typical, 2 μs maximum New values: 35 ns typical , 45 ns maximum Rev. 2 Rev. 3 In Table 10-20, changed the maxim.


Freescale Semiconductor 56F8036

um ADC internal clock frequency from 8MH z to 5.33MHz. Added the following note to the description of the TMS signal in Table 2-3: Note: Always tie the TMS pi n to VDD through a 2.2K resistor. Descr iption of Change Please see http://www .freescale.com for the most current Dat a Sheet revision. 56F8036 Data Sheet, Rev. 3 2 Freescale Semiconductor Prelim inary 56F8036 Gen.


Freescale Semiconductor 56F8036

eral Description • Up to 32 MIPS at 32 MHz core frequency • DSP and MCU func tionality in a unified, C-efficient arc hitecture • 64KB (32K x 16) Program F lash • 8KB (4K x 16) Unified Data/Pro gram RAM • One 6-channel PWM module c locked at up to 96MHz • Two independe nt 5-channel 12-bit high-speed Analog-t o-Digital Converters (ADCs) • Two int ernal 12-bit Digital-to-Analog C.





Part

56F8036

Description

16-bit Digital Signal Controllers



Feature


www.DataSheet4U.com 56F8036 Data Sheet Preliminary Technical Data 56F8000 16- bit Digital Signal Controllers MC56F80 36 Rev. 3 01/2007 freescale.com Docum ent Revision History Version History Re v. 0 Rev. 1 Initial public release. • In Table 10-4, added an entry for flas h data retention with less than 100 pro gram/erase cycles (minimum 20 years). In Table 10-6, chan.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F8036 Datasheet




 56F8036
www.DataSheet4U.com
56F8036
Data Sheet
Preliminary Technical Data
56F8000
16-bit Digital Signal Controllers
MC56F8036
Rev. 3
01/2007
freescale.com




 56F8036
Version History
Rev. 0
Rev. 1
Rev. 2
Rev. 3
Document Revision History
Description of Change
Initial public release.
• In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-21 as follows:
Old values: 1 μs typical, 2 μs maximum
New values: 35 ns typical, 45 ns maximum
In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.
Added the following note to the description of the TMS signal in Table 2-3:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
Please see http://www.freescale.com for the most current Data Sheet revision.
56F8036 Data Sheet, Rev. 3
2
Freescale Semiconductor
Preliminary




 56F8036
56F8036 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 64KB (32K x 16) Program Flash
• 8KB (4K x 16) Unified Data/Program RAM
• One 6-channel PWM module clocked at up to 96MHz
• Two independent 5-channel 12-bit high-speed
Analog-to-Digital Converters (ADCs)
• Two internal 12-bit Digital-to-Analog Converters
(DACs)
• Two Analog Comparators
• Three Programmable Interval Timers (PITs)
• One Queued Serial Communication Interface (QSCI)
with LIN slave functionality
• One Queued Serial Peripheral Interface (QSPI)
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• One 16-bit Quad Timer clocked at up to 96MHz
• One Inter-Integrated Circuit (I2C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 39 GPIO lines
• 48-pin LQFP Package
RESET or
GPIOA
4
VCAP
2
VDD
2
VSS
3
VDDA VSSA
11 PWM
or TMRA or CMP
or GPIOA
JTAG/EOnCE
Port or
GPIOD
Digital Reg Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Program Controller
and Hardware
Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
DAC
5 AD0
ADC
or CMP
or GPIOC
5 AD1
Memory
Program Memory
32K x 16 Flash
Unified Data /
Program RAM
4K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
PAB
PDB
CDBR
CDBW
R/W Control
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I2C
or CAN
or CMP
or GPIOB
4
QSPI
or PWM
or I2C
or TMRA
or GPIOB
4
QSCI
or PWM
or I2C
or TMRA
or GPIOB
3
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
Clock
Generator*
O
S
C
*Includes On-Chip
Relaxation Oscillator
56F8036 Block Diagram
Freescale Semiconductor
Preliminary
56F8036 Data Sheet, Rev. 3
XTAL, CLKIN, or
GPIOD
EXTAL or GPIOD
3




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