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Signal Controllers. 56F8147 Datasheet

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Signal Controllers. 56F8147 Datasheet
















56F8147 Controllers. Datasheet pdf. Equivalent













Part

56F8147

Description

16-bit Digital Signal Controllers



Feature


56F8347/56F8147 Data Sheet Preliminary T echnical Data 56F8300 16-bit Digital Si gnal Controllers MC56F8347 Rev.11 01/20 07 freescale.com Version History Rev 0 Rev 1.0 Rev 2.0 Rev 3.0 Rev 4.0 Rev 5. 0 Rev 6.0 Rev 7.0 Rev 8.0 Rev 9.0 Rev 1 0.0 Rev. 11 Document Revision History Description of Change Initial release F ixed typos in Section 1.1.3, Replace an y reference to Fla.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F8147 Datasheet


Freescale Semiconductor 56F8147

56F8147; sh Interface Unit with Flash Module, cor rected pin number for D14 in Table 2-2, added note to Vcap pin in Table 2-2, c orrected thermal numbers for 160 LQFP i n Table 10-4,removed unneccessary notes in Table 10-13; corrected temperature range in Table 10-14; added ADC calibra tion information to Table 10-24 and new graphs in Figure 10-22. Clarification to Table 10-23, co.


Freescale Semiconductor 56F8147

rrected Digital Input Current Low (pull- up enabled) numbers in Table 10-5. Remo ved text and Table 10-2; replaced with note to Table 10-1. Added 56F8147 infor mation; edited to indicate differences in 56F8347 and 56F8147. Reformatted for Freescale look and feel. .


Freescale Semiconductor 56F8147

.





Part

56F8147

Description

16-bit Digital Signal Controllers



Feature


56F8347/56F8147 Data Sheet Preliminary T echnical Data 56F8300 16-bit Digital Si gnal Controllers MC56F8347 Rev.11 01/20 07 freescale.com Version History Rev 0 Rev 1.0 Rev 2.0 Rev 3.0 Rev 4.0 Rev 5. 0 Rev 6.0 Rev 7.0 Rev 8.0 Rev 9.0 Rev 1 0.0 Rev. 11 Document Revision History Description of Change Initial release F ixed typos in Section 1.1.3, Replace an y reference to Fla.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F8147 Datasheet




 56F8147
56F8347/56F8147
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8347
Rev.11
01/2007
freescale.com




 56F8147
Version History
Rev 0
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev. 11
Document Revision History
Description of Change
Initial release
Fixed typos in Section 1.1.3, Replace any reference to Flash Interface Unit with Flash Module,
corrected pin number for D14 in Table 2-2, added note to Vcap pin in Table 2-2, corrected
thermal numbers for 160 LQFP in Table 10-4,removed unneccessary notes in Table 10-13;
corrected temperature range in Table 10-14; added ADC calibration information to Table 10-24
and new graphs in Figure 10-22.
Clarification to Table 10-23, corrected Digital Input Current Low (pull-up enabled)
numbers in Table 10-5. Removed text and Table 10-2; replaced with note to Table 10-1.
Added 56F8147 information; edited to indicate differences in 56F8347 and 56F8147.
Reformatted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updaated balance of electrical tables for consistency throughout the family. Clarified I/O power
description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
Correcting Figure 4-1 Boot Flash Start = $02_0000
Added output voltage maximum value and note to clarify in Table 10-1; also removed overall life
expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed PD
in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4.
Added new RoHS-compliant orderable part numbers in Table 13-1.
Added 160MAPBGA information, TA equation updated in Table 10-4 and additional minor edits
throughout data sheet
Updated Table 10-24 to reflect new value for maximum Uncalibrated Gain Error
Deleted formula for Max Ambient Operating Temperature (Automotive) and Max Ambient
Operating Temperature (Industrial) and corrected Flash Endurance to 10,000 in Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Corrected Section 6.4 title (from Operation Mode Register to Operating Mode Register).
Updated JTAG ID in Section 6.5.4. Added information/corrected state during reset in Table 2-2.
Clarified external reference crystal frequency for PLL in Table 10-14 by increasing maximum
value to 8.4MHz.
Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2.
• Added the following note to the description of the TMS signal in Table 2-2:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Added the following note to the description of the TRST signal in Table 2-2:
Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging
environment, TRST may be tied to VSS through a 1K resistor.
Please see http://www.freescale.com for the most current data sheet revision.
56F8347 Technical Data, Rev.11
2 Freescale Semiconductor
Preliminary




 56F8147
56F8347/56F8147 General Description
Note: Features in italics are NOT available in the 56F8147 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 4MB of off-chip program and 32MB of
data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 8KB of Data RAM
• 8KB of Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 76 GPIO lines
• 160-pin LQFP Package and 160MAPBGA
RSTO EMI_MODE
RESET EXTBOOT
OCR_DIS
VPP VCAP* VDD
VSS
VDDA VSSA
52
47
62
* Configuration
shown for on-chip
2.5V regulator
6 PWM Outputs
PWMA
3 Current Sense Inputs or GPIOC
4 Fault Inputs
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
6 PWM Outputs
PWMB
3 Current Sense Inputs or GPIOD
4 Fault Inputs
4 AD0
4 AD1 ADCA
5 VREF
4
4
AD0 ADCB
AD1
Memory
Program Memory
Temp_Sense
64K x 16 Flash
2K x 16 RAM
Quadrature
4
Decoder 0 or
Quad
Boot ROM
4K x 16 Flash
Timer A or
Data Memory
GPIOC
4K x 16 RAM
4K x 16 Flash
Quadrature
4
Decoder 1 or
Quad
Timer B or
SPI1 or GPIOC
2
Quad
Timer C or
Decoding
2
GPIOE
Quad
Peripherals
Timer D or
GPIOE
Program Controller
and
Hardware Looping Unit
PAB
PDB
CDBR
CDBW
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
Address
Generation Unit
Data ALU
16 x 16 + 36 Æ 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
R/W Control
System Bus
Control
IPBus Bridge (IPBB)
Peripheral
Device Selects
RW IPAB
Control
IPWDB IPRDB
Clock
resets
Bit
Manipulation
Unit
External
Address Bus
Switch
6
2
8
4
1
3
External Data 7
Bus Switch 9
Bus Control 6
PLL
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0-3 (A16-19)
GPIOB4 (A20,
prescaler_clock)
GPIOB5-7 (A21-23,
clk0-3**)
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-5 or CS2-7
PS (CS0 or GPIOD8)
DS (CS1 or GPIOD9)
**See Table 2-2
for explanation
2 FlexCAN
SPI0 or SCI1 or SCI0 or COP/
GPIOE GPIOD GPIOE Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
Clock O
Generator
S
C
XTAL
EXTAL
4 22
IRQA
IRQB
CLKO CLKMODE
56F8347/56F8147 Block Diagram
Freescale Semiconductor
Preliminary
56F8347 Technical Data, Rev.11
3




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