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Signal Controllers. 56F8156 Datasheet

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Signal Controllers. 56F8156 Datasheet
















56F8156 Controllers. Datasheet pdf. Equivalent













Part

56F8156

Description

(56F8156 / 56F8356) 16-bit Digital Signal Controllers



Feature


www.DataSheet4U.com 56F8356/56F8156 Dat a Sheet Preliminary Technical Data 56F 8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.c om Document Revision History Version H istory Rev 1.0 Rev 2.0 Initial Public R elease Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table 10-18. Editi.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F8156 Datasheet


Freescale Semiconductor 56F8156

56F8156; ng grammar, spelling, consistency of lan guage throughout family. Updated values in Regulator Parameters Table 10-9, Ex ternal Clock Operation Timing Requireme nts Table 10-13, SPI Timing Table 10-18 , ADC Parameters Table 10-24, and IO Lo ading Coefficients at 10MHz Table 10-25 . Added Part 4.8, added the word “acc ess” to FM Error Interrupt in Table 4 -5, documenting only T.


Freescale Semiconductor 56F8156

yp. numbers for LVI in Table 10-6, updat ed EMI numbers and writeup in Part 10.8 . Updated numbers in Table 10-7 and Tab le 10-8 with more recent data, Correcte d typo in Table 10-3 in Pd characterist ics. Replace any reference to Flash Int erface Unit with Flash Memory Module; c orrected thermal numbers for 144 LQFP i n Table 10-3; removed unneccessary note s in Table 10-12; .


Freescale Semiconductor 56F8156

corrected temperature range in Table 10- 14; added ADC calibration information t o Table 10-24 and new graphs in Figure 10-22 Adding/clarifing notes to Table 4 -4 to help clarify independent program flash blocks and other Program Flash mo des, clarification to Table 10-23, corr ected Digital Input Current Low (pull-u p enabled) numbers in Table 10-5. Remov ed text and Table .





Part

56F8156

Description

(56F8156 / 56F8356) 16-bit Digital Signal Controllers



Feature


www.DataSheet4U.com 56F8356/56F8156 Dat a Sheet Preliminary Technical Data 56F 8300 16-bit Digital Signal Controllers MC56F8356 Rev. 13 01/2007 freescale.c om Document Revision History Version H istory Rev 1.0 Rev 2.0 Initial Public R elease Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added “Typical Min” values to Table 10-18. Editi.
Manufacture

Freescale Semiconductor

Datasheet
Download 56F8156 Datasheet




 56F8156
www.DataSheet4U.com
56F8356/56F8156
Data Sheet
Preliminary Technical Data
56F8300
16-bit Digital Signal Controllers
MC56F8356
Rev. 13
01/2007
freescale.com




 56F8156
Document Revision History
Version History
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev 11.0
Rev 12.0
Rev. 13
Description of Change
Initial Public Release
Added Package Pins to GPIO Table in Part 8 General Purpose Input/Output (GPIO). Added
“Typical Min” values to Table 10-18. Editing grammar, spelling, consistency of language
throughout family. Updated values in Regulator Parameters Table 10-9, External Clock
Operation Timing Requirements Table 10-13, SPI Timing Table 10-18, ADC Parameters
Table 10-24, and IO Loading Coefficients at 10MHz Table 10-25.
Added Part 4.8, added the word “access” to FM Error Interrupt in Table 4-5, documenting only
Typ. numbers for LVI in Table 10-6, updated EMI numbers and writeup in Part 10.8.
Updated numbers in Table 10-7 and Table 10-8 with more recent data, Corrected typo in
Table 10-3 in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module; corrected thermal
numbers for 144 LQFP in Table 10-3; removed unneccessary notes in Table 10-12; corrected
temperature range in Table 10-14; added ADC calibration information to Table 10-24 and new
graphs in Figure 10-22
Adding/clarifing notes to Table 4-4 to help clarify independent program flash blocks and other
Program Flash modes, clarification to Table 10-23, corrected Digital Input Current Low (pull-up
enabled) numbers in Table 10-5. Removed text and Table 10-2; replaced with note to
Table 10-1.
Added 56F8156 information; edited to indicate differences in 56F8356 and 56F8156. Refor-
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout family. Clarified I/O power
description in Table 2-2, added note to Table 10-7 and clarified Section 12.3.
Added output voltage maximum value and note to clarify in Table 10-1; also removed overall
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
PD in Table 10-3. Corrected note about average value for Flash Data Retention in Table 10-4.
Added new RoHS-compliant orderable part numbers in Table 13-1.
Updated Table 10-24 to reflect new value for maximum Uncalibrated Gain Error
Deleted RSTO from Pin Group 2 (listed after Table 10-1). Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4. Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in Table 2-2. Clarified external reference crys-
tal frequency for PLL in Table 10-14 by increasing maximum value to 8.4MHz..
Replaced “Tri-stated” with an explanation in State During Reset column in Table 2-2.
• Added the following note to the description of the TMS signal in Table 2-2:
Note: Always tie the TMS pin to VDD through a 2.2K resistor.
• Added the following note to the description of the TRST signal in Table 2-2:
Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging
environment, TRST may be tied to VSS through a 1K resistor.
Please see http://www.freescale.com for the most current data sheet revision.
56F8356 Technical Data, Rev. 13
2 Freescale Semiconductor
Preliminary




 56F8156
56F8356/56F8156 General Description
Note: Features in italics are NOT available in the 56F8156 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB of Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package
RSTO EMI_MODE
RESET EXTBOOT
5
VPP VCAP
OCR_DIS
VDD
Vss
24 7 5
VDDA
2
VSSA
3
6 PWM Outputs
Current Sense Inputs
PWMA
3
or GPIOC
Fault Inputs
JTAG/
EOnCE
Port
Digital Reg Analog Reg
16-Bit
Low Voltage
56800E Core Supervisor
6 PWM Outputs
3 Current Sense Inputs
4
or GPIOD
Fault Inputs
4 AD0
4
ADCA
AD1
PWMB
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
PAB
PDB
CDBR
CDBW
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Bit
Manipulation
Unit
5 VREF
Memory
4
4
AD0 Program Memory
ADCB 128K x 16 Flash
AD1 2K x 16 RAM
XDB2
XAB1
XAB2
TEMP_SENSE 8K x 16 Boot
Quadrature
Flash
4
Decoder 0 or
Quad
Timer A or
GPIOC
Data Memory
4K x 16 Flash
8K x 16 RAM
PAB
PDB
CDBR
CDBW
R/W Control
External
Address Bus
Switch
6
2
8
System Bus
Control
External Data
Bus Switch
7
9
Quadrature
Decoder 1 or
4 Quad
Timer B or
IPBus Bridge (IPBB)
SPI1 or
GPIOC
Quad
Decoding
Peripheral
Device Selects
RW IPAB
Control
IPWDB
IPRDB
1
Timer C or
GPIOE
Peripherals
Bus Control 2
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
GPIOD0-1 or CS2-3
PS or CS0 or GPIOD8
DS or CS1 or GPIOD9
2
Quad
Timer D or
Clock
resets
PLL
GPIOE
2
FlexCAN
SPI0 or
GPIOE
SCI1 or
GPIOD
SCI0 or
COP/
Interrupt
GPIOE Watchdog Controller
System
Integration
P
O
R
Module
Clock
Generator
O
S
C
XTAL
EXTAL
42 2
IRQA IRQB
CLKO CLKMODE
56F8356 / 56F8156 Block Diagram
Freescale Semiconductor
Preliminary
56F8356 Technical Data, Rev. 13
3




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