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Configurable UART. D16550 Datasheet

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Configurable UART. D16550 Datasheet
















D16550 UART. Datasheet pdf. Equivalent













Part

D16550

Description

Configurable UART



Feature


www.DataSheet4U.com D16550 Configurable UART with FIFO ver 2.11 OVERVIEW The D 16550 is a soft Core of a Universal Asy nchronous Receiver/Transmitter (UART) f unctionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activat ed allowing 16 bytes (plus 3 bits of er ror data per byte .
Manufacture

Lattice Semiconductor

Datasheet
Download D16550 Datasheet


Lattice Semiconductor D16550

D16550; in the RCVR FIFO) to be stored in both r eceive and transmit directions. D16550 performs serial-toparallel conversion o n data characters received from a perip heral device or a MODEM, and parallel-t o-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information.


Lattice Semiconductor D16550

reported includes the type and conditio n of the transfer operations being perf ormed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16550 includes a programmable baud rate generator that i s capable of dividing the timing refere nce clock input by divisors of 1 to (21 6-1), and producing a 16 × clock for d riving the internal.


Lattice Semiconductor D16550

transmitter logic. Provisions are also included to use this 16 × clock to dri ve the receiver logic. The D16550 has c omplete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requir ements, minimizing the computing requir ed to handle the communications link. T he separate BAUD CLK line allow to set an exact transmissi.





Part

D16550

Description

Configurable UART



Feature


www.DataSheet4U.com D16550 Configurable UART with FIFO ver 2.11 OVERVIEW The D 16550 is a soft Core of a Universal Asy nchronous Receiver/Transmitter (UART) f unctionally identical to the TL16C550A. The D16550 allows serial transmission in two modes: UART mode and FIFO mode. In FIFO mode internal FIFOs are activat ed allowing 16 bytes (plus 3 bits of er ror data per byte .
Manufacture

Lattice Semiconductor

Datasheet
Download D16550 Datasheet




 D16550
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D16550
Configurable UART with FIFO
ver 2.11
OVERVIEW
The D16550 is a soft Core of a Universal
Asynchronous Receiver/Transmitter (UART)
functionally identical to the TL16C550A. The
D16550 allows serial transmission in two
modes: UART mode and FIFO mode. In FIFO
mode internal FIFOs are activated allowing 16
bytes (plus 3 bits of error data per byte in the
RCVR FIFO) to be stored in both receive and
transmit directions. D16550 performs serial-to-
parallel conversion on data characters
received from a peripheral device or a
MODEM, and parallel-to-serial conversion on
data characters received from the CPU. The
CPU can read the complete status of the
UART at any time during the functional
operation. Status information reported
includes the type and condition of the transfer
operations being performed by the UART, as
well as any error conditions (parity, overrun,
framing, or break interrupt). D16550 includes
a programmable baud rate generator that is
capable of dividing the timing reference clock
input by divisors of 1 to (216-1), and producing
a 16 × clock for driving the internal transmitter
logic. Provisions are also included to use this
16 × clock to drive the receiver logic. The
D16550 has complete MODEM control
capability, and a processor-interrupt system.
Interrupts can be programmed to the user's
requirements, minimizing the computing
required to handle the communications link.
The separate BAUD CLK line allow to set an
exact transmission speed, while the UART
All trademarks mentioned in this document
are trademarks of their respective owners.
internal logic is clocked with the CPU
frequency.
Two DMA modes are supported: single
transfer and multi-transfer. These modes
allow UART to interface to higher performance
DMA units, which can interleave their
transfers between CPU cycles or execute
multiple byte transfers.
The configuration capability allows user to
enable or disable during Synthesis process
the Modem Control Logic and FIFO's Control
Logic, change the FIFO size. So in
applications with area limitation and where the
UART works only in 16450 mode, disabling
Modem Control and FIFO's allow to save
about 50% of logic resources.
The D16550 has universal microcontroller
interface, allows correct communication with
D16550 no matter how D16550 clock is
related to microcontroller clock. The core is
perfect for applications, where the UART Core
and microcontroller are clocked by the same
clock signal and are implemented inside the
same ASIC or FPGA chip, as well as for
standalone implementation, where several
UARTs are required to be implemented inside
a single chip, and driven by some off-chip
devices. Thanks to universal interface D16550
core implementation and verification are very
simply, by eliminating a number of clock trees
in complete system.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.




 D16550
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APPLICATIONS
Serial Data communications applications
Modem interface
KEY FEATURES
Software compatible with 16450 and
16550 UARTs
Configuration capability
Separate configurable BAUD clock line
Two modes of operation: UART mode and
FIFO mode
Majority Voting Logic
In the FIFO mode transmitter and receiver
are each buffered with 16 byte FIFO to
reduce the number of interrupts presented
to the CPU
Adds or deletes standard asynchronous
communication bits (start, stop, and parity)
to or from the serial data
In UART mode receiver and transmitter
are double buffered to eliminate a need for
precise synchronization between the CPU
and serial data
Independently controlled transmit, receive,
line status, and data set interrupts
False start bit detection
16 bit programmable baud generator
MODEM control functions (CTS, RTS,
DSR, DTR, RI, and DCD)
Fully programmable
characteristics:
serial-interface
5-, 6-, 7-, or 8-bit characters
Even, odd, or no-parity bit generation and
detection
1-, 1½-, or 2-stop bit generation
Baud generation
Complete status reporting capabilities
Line break generation and detection.
Internal diagnostic capabilities:
Loop-back controls for communications link
fault isolation
Break, parity, overrun, framing error
simulation
Two DMA Modes allows single and multi-
transfer
All trademarks mentioned in this document
are trademarks of their respective owners.
Technology independent HDL Source
Code
Full prioritized interrupt system controls
Fully synthesizable static design with no
internal tri-state buffers
DESIGN FEATURES
The functionality of the D16550 core was
based on the Texas Instruments TL16C550A.
The following characteristics differentiate the
D16550 from Texas Instruments devices:
The bi-directional data bus has been split
into two separate buses: datai(7:0),
datao(7:0)
Signals rd2 and wr2, xin, and xout have
been removed from interface
Signal ADS and address latch have been
removed
The DLL, DLM and THR registers are
reset to all zeros
TEMT and THRE bits of Line Status
Register, are reset during the second
clock rising edge following a THR write
RCLK clock is replaced by global clock
CLK, internally divided by BAUD factor.
Asynchronous microcontroller interface is
replaced by equivalent Universal interface
All latches implemented in original 16550
devices are replaced by equivalent flip-flop
registers, with the same functionality
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.




 D16550
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DELIVERABLES
Source code:
VHDL Source Code or/and
VERILOG Source Code or/and
Encrypted, or plain text EDIF netlist
VHDL & VERILOG test bench
environment
Active-HDL automatic simulation macros
ModelSim automatic simulation macros
Tests with reference responses
Technical documentation
Installation notes
HDL core specification
Datasheet
Synthesis scripts
Example application
Technical support
IP Core implementation support
3 months maintenance
Delivery the IP Core updates, minor
and major versions changes
Delivery the documentation updates
Phone & email support
LICENSING
Comprehensible and clearly defined licensing
methods without royalty fees make using of IP
Core easy and simply.
Single Design license allows use IP Core in
single FPGA bitstream and ASIC
implementation.
Unlimited Designs, One Year licenses allow
use IP Core in unlimited number of FPGA
bitstreams and ASIC implementations.
In all cases number of IP Core instantiations
within a design, and number of manufactured
chips are unlimited. There is no time
restriction except One Year license where
time of use is limited to 12 months.
Single Design license for
VHDL, Verilog source code called HDL
Source
Encrypted, or plain text EDIF called Netlist
One Year license for
Encrypted Netlist only
Unlimited Designs license for
HDL Source
Netlist
Upgrade from
HDL Source to Netlist
Single Design to Unlimited Designs
CONFIGURATION
The following parameters of the D16550 core
can be easy adjusted to requirements of
dedicated application and technology.
Configuration of the core can be prepared by
effortless changing appropriate constants in
package file. There is no need to change any
parts of the code.
Baud generator
- enable
- disable
External RCLK source
- enable
- disable
External BAUDCLK source
- enable
- disable
Modem Control logic
- enable
- disable
SCR Register
- enable
- disable
FIFO Control logic
- enable
- disable
APPLICATION
addr
CPU ale
datao(7:0)
datai(7:0)
we
rd
cs
int
addr
latch
addr(2:0)
D16550
clk
rst
baudclk
rclk
datai(7:0)
so
datao(7:0)
si
wr rts
rd dtr
cs dsr
intr dcd
cts
rxrdy
ri
txrdy
out1 baudclken
out2 rclken
EIA
Drivers
Typical D16550 and processor connection is
shown in figure above.
All trademarks mentioned in this document
are trademarks of their respective owners.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.




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