DatasheetsPDF.com

nanoDAC. AD5044 Datasheet

DatasheetsPDF.com

nanoDAC. AD5044 Datasheet
















AD5044 nanoDAC. Datasheet pdf. Equivalent













Part

AD5044

Description

nanoDAC



Feature


Data Sheet Fully Accurate, 12-/14-/16-B it VOUT nanoDAC, Quad, SPI Interface, 4 .5 V to 5.5 V in TSSOP AD5024/AD5044/AD 5064 FEATURES Low power quad 12-/14-/1 6-bit DAC, ±1 LSB INL Pin compatible a nd performance upgrade to AD5666 Indivi dual and common voltage reference pin o ptions Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to ze ro scale or midscal.
Manufacture

Analog Devices

Datasheet
Download AD5044 Datasheet


Analog Devices AD5044

AD5044; e 3 power-down functions and per-channel power-down Hardware LDAC with software LDAC override function CLR function to programmable code SDO daisy-chaining o ption 14-/16-lead TSSOP Internal refere nce buffer and internal output amplifie r APPLICATIONS Process control Data acq uisition systems Portable battery-power ed instruments Digital gain and offset adjustment Program.


Analog Devices AD5044

mable voltage and current sources Progra mmable attenuators GENERAL DESCRIPTION The AD5024/AD5044/AD5064/AD5064-1 are l ow power, quad 12-/14-/16-bit buffered voltage output nanoDAC® converters tha t offer relative accuracy specification s of 1 LSB INL and 1 LSB DNL with the A D5024/AD5044/AD5064 individual referenc e pin and the AD5064-1 common reference pin options. The A.


Analog Devices AD5044

D5024/AD5044/AD5064/AD5064-1 can operate from a single 4.5 V to 5.5 V supply. T he AD5024/AD5044/AD5064/AD5064-1 also o ffer a differential accuracy specificat ion of ±1 LSB. The devices use a versa tile 3-wire, low power Schmitt trigger serial interface that operates at clock rates up to 50 MHz and is compatible w ith standard SPI, QSPI™, MICROWIRE, a nd DSP interface stan.





Part

AD5044

Description

nanoDAC



Feature


Data Sheet Fully Accurate, 12-/14-/16-B it VOUT nanoDAC, Quad, SPI Interface, 4 .5 V to 5.5 V in TSSOP AD5024/AD5044/AD 5064 FEATURES Low power quad 12-/14-/1 6-bit DAC, ±1 LSB INL Pin compatible a nd performance upgrade to AD5666 Indivi dual and common voltage reference pin o ptions Rail-to-rail operation 4.5 V to 5.5 V power supply Power-on reset to ze ro scale or midscal.
Manufacture

Analog Devices

Datasheet
Download AD5044 Datasheet




 AD5044
Data Sheet
Fully Accurate, 12-/14-/16-Bit VOUT nanoDAC, Quad,
SPI Interface, 4.5 V to 5.5 V in TSSOP
AD5024/AD5044/AD5064
FEATURES
Low power quad 12-/14-/16-bit DAC, ±1 LSB INL
Pin compatible and performance upgrade to AD5666
Individual and common voltage reference pin options
Rail-to-rail operation
4.5 V to 5.5 V power supply
Power-on reset to zero scale or midscale
3 power-down functions and per-channel power-down
Hardware LDAC with software LDAC override function
CLR function to programmable code
SDO daisy-chaining option
14-/16-lead TSSOP
Internal reference buffer and internal output amplifier
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5024/AD5044/AD5064/AD5064-1 are low power, quad
12-/14-/16-bit buffered voltage output nanoDAC® converters
that offer relative accuracy specifications of 1 LSB INL and 1 LSB
DNL with the AD5024/AD5044/AD5064 individual reference
pin and the AD5064-1 common reference pin options. The
AD5024/AD5044/AD5064/AD5064-1 can operate from a single
4.5 V to 5.5 V supply. The AD5024/AD5044/AD5064/AD5064-1
also offer a differential accuracy specification of ±1 LSB. The
devices use a versatile 3-wire, low power Schmitt trigger serial
interface that operates at clock rates up to 50 MHz and is compati-
ble with standard SPI, QSPI™, MICROWIRE, and DSP interface
standards. Integrated reference buffers and output amplifiers are
also provided on-chip. The AD5024/AD5044/AD5064/AD5064-1
incorporate a power-on reset circuit that ensures the DAC
output powers up to zero scale or midscale and remains there
until a valid write takes place to the device. The AD5024/AD5044/
AD5064/AD5064-1 contain a power-down feature that reduces
the current consumption of the device to typically 400 nA at 5 V
and provides software selectable output loads while in power-
down mode. Total unadjusted error for the devices is <2 mV.
FUNCTIONAL BLOCK DIAGRAMS
VDD
VREFIN
AD5064-1
SCLK
SYNC
DIN
SDO
LDAC
INTERFACE
LOGIC AND
SHIFT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
VOUTA
BUFFER
VOUTB
BUFFER
VOUTC
BUFFER
VOUTD
POWER-DOWN
LOGIC
LDAC CLR
POR
GND
Figure 1. AD5064-1 Functional Equivalent and Pin Compatible with AD5666
AD5024/
AD5044/
AD5064 LDAC
SCLK
SYNC
DIN
INTERFACE
LOGIC AND
SHIFT
REGISTER
VDD
VREFA VREFB
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
POWER-ON
RESET
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC A
DAC B
DAC C
DAC D
BUFFER
BUFFER
BUFFER
BUFFER
POWER-DOWN
LOGIC
VOUTA
VOUTB
VOUTC
VOUTD
LDAC CLR
POR
VREFC VREFD
GND
Figure 2. AD5024/AD5044/AD5064 with Individual Reference Pins
PRODUCT HIGHLIGHTS
1. Quad channel available in 14-/16-lead TSSOPs.
2. 16-bit accurate, 1 LSB INL.
3. High speed serial interface with clock speeds up to 50 MHz.
4. Reset to known output voltage (zero scale or midscale).
Table 1. Related Devices
Device No.
AD5666
AD5025/AD5045/AD5065
AD5062, AD5063
AD5061
AD5040/AD5060
Description
Quad,16-bit buffered DAC,
16 LSB INL, TSSOP
Dual, 16-bit buffered DACs,
1 LSB INL, TSSOP
16-bit nanoDAC, 1 LSB INL, SOT-23,
MSOP
16-bit nanoDAC, 4 LSB INL, SOT-23
14-/16-bit nanoDAC, 1 LSB INL,
SOT-23
Rev. G
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




 AD5044
AD5024/AD5044/AD5064
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
Functional Block Diagrams............................................................. 1 
General Description ......................................................................... 1 
Product Highlights ........................................................................... 1 
Revision History ............................................................................... 2 
Specifications..................................................................................... 3 
AC Characteristics........................................................................ 4 
Timing Characteristics ................................................................ 5 
Absolute Maximum Ratings............................................................ 7 
ESD Caution.................................................................................. 7 
Pin Configurations and Function Descriptions ........................... 8 
Typical Performance Characteristics ........................................... 10 
Terminology .................................................................................... 17 
Theory of Operation ...................................................................... 19 
Digital-to-Analog Converter .................................................... 19 
DAC Architecture....................................................................... 19 
Reference Buffer ......................................................................... 19 
REVISION HISTORY
6/2016—Rev. F to Rev. G
Changed ADSP-BF53x to ADSP-BF527..................... Throughout
Changes to Power-On Reset Section............................................ 22
6/2013—Rev. E to Rev. F
Change to Standalone Mode Section ........................................... 21
5/2011—Rev. D to Rev. E
Changes to Table 4............................................................................ 5
Changes to Figure 4 and Figure 5................................................... 6
8/20—Rev. C to Rev. D
Change to Minimum SYNC High Time (Single Channel
Update) Parameter, Table 4 ............................................................. 5
5/2010—Rev. B to Rev. C
Changes to Power-On Reset Section............................................ 22
6/2009—Rev. A to Rev. B
Changes to Figure 1.......................................................................... 1
3/2009—Rev. 0 to Rev. A
Added 14-Lead TSSOP ......................................................Universal
Added Figure 1; Renumbered Sequentially .................................. 1
Changes to Features Section, General Description Section,
Product Highlights Section, Figure 2, and Table 1....................... 1
Changes to Table 2............................................................................ 3
Output Amplifier........................................................................ 19 
Serial Interface ............................................................................ 19 
Shift Register ............................................................................... 19 
Modes of Operation ................................................................... 21 
Power-On Reset.......................................................................... 22 
Power-Down Modes .................................................................. 22 
Clear Code Register ................................................................... 23 
LDAC Function .......................................................................... 23 
Power Supply Bypassing and Grounding................................ 24 
Microprocessor Interfacing....................................................... 25 
Applications Information .............................................................. 26 
Using a Reference as a Power Supply....................................... 26 
Bipolar Operation....................................................................... 26 
Using the AD5024/AD5044/AD5064/AD5064-1 with a
Galvanically Isolated Interface ................................................. 26 
Outline Dimensions ....................................................................... 27 
Ordering Guide .......................................................................... 28 
Changes to Timing Characteristics Section and Table 4..............5
Added Circuit and Timing Diagrams Section and Figure 3........5
Added Figure 5...................................................................................6
Changes to Figure 4...........................................................................6
Added Figure 6...................................................................................8
Added Table 6; Renumbered Sequentially .....................................8
Changed Input Shift Register to Shift Register Throughout .......8
Changes to Table 7.............................................................................9
Changes to Typical Performance Characteristics Section ........ 10
Changes to Terminology Section ................................................. 17
Changes to Digital-to-Analog Converter Section, Reference
Buffer Section, Output Amplifier Section, Serial Interface
Section, Shift Register Section, and Table 8 ................................ 19
Changes to Figure 47, Figure 48, and Figure 49 Captions ........ 20
Added Modes of Operation Section, Daisy-Chaining Section,
Table 10, and Table 11.................................................................... 21
Changes to Table 13 and Power-Down Mode Section .............. 22
Changes to Table 16 ....................................................................... 24
Changes to Figure 52 to Figure 55................................................ 25
Changes to Bipolar Operation Section and Figure 56 to
Figure 58 .......................................................................................... 26
Added Figure 59 ............................................................................. 27
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide .......................................................... 28
8/2008—Revision 0: Initial Version
Rev. G | Page 2 of 28




 AD5044
Data Sheet
AD5024/AD5044/AD5064
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, RL = 5 kΩ to GND, CL = 200 pF to GND, 2.5 V ≤ VREFIN ≤ VDD, unless otherwise specified. All specifications TMIN to
TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE3
Resolution
Relative Accuracy (INL)4
Min
16
14
12
Differential Nonlinearity (DNL)4
Total Unadjusted Error
Offset Error4, 5
Offset Error Temperature
Coefficient4, 6
Full-Scale Error4
Gain Error4
Gain Temperature Coefficient4, 6
DC Crosstalk4, 6
OUTPUT CHARACTERISTICS6
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Normal Mode
Power-Down Mode
Output Connected to
100 kΩ Network
Output Connected to
1 kΩ Network
Short-Circuit Current
Power-Up Time7
DC PSRR
REFERENCE INPUTS
Reference Input Range
Reference Current
0
2.2
Reference Input Impedance
LOGIC INPUTS
Input Current8
Input Low Voltage, VINL
Input High Voltage, VINH
Pin Capacitance6
2.2
B Grade1
Typ Max
A Grade1, 2
Min Typ Max
Unit
Test Conditions/Comments
16
±0.5
±0.5
±0.25
±0.12
±0.2
±0.2
±2
±1
±2
±1
±0.5
±1
±2
±1.8
±0.01
±0.005
±1
±0.07
±0.05
40
40
40
Bits AD5064/AD5064-1
Bits AD5044
Bits AD5024
±0.5 ±4 LSB AD5064/AD5064-1; TA = −40°C to +105°C
±0.5 ±4 LSB AD5064/AD5064-1; TA = −40°C to +125°C
LSB AD5044
LSB AD5024
±0.2 ±1
LSB
±2 mV
VREF = 2.5 V, VDD = 5.5 V
±0.2 ±1.8 mV
±2 μV/°C
±0.01
±0.005
±1
±0.07
±0.05
40
40
40
% FSR
% FSR
ppm
FSR/°C
μV
μV/mA
μV
All 1s loaded to DAC register, VREF < VDD
VREF < VDD
Due to single-channel, full-scale output
change, RL = 5 kΩ to GND or VDD
Due to load current change
Due to powering down (per channel)
VDD 0
1
0.5
VDD V
1 nF
RL = 5 kΩ, RL =100 kΩ, and RL = ∞
0.5 Ω
100 100 kΩ Output impedance tolerance ± 20 kΩ
1 1 kΩ Output impedance tolerance ± 400 Ω
60 60 mA DAC = full scale, output shorted to GND
45 45 mA DAC = zero scale, output shorted to VDD
4.5 4.5 μs
−92 −92 dB VDD ± 10%, DAC = full scale, VREF < VDD
VDD 2.2
35 50
140 160
120
32
VDD V
35 50 μA
140 160 μA
120 kΩ
32 kΩ
Per DAC channel; individual reference
option
Single reference option
Individual reference option
Single reference option
±1 ±1 μA
0.8 0.8 V
2.2 V
4 4 pF
Rev. G | Page 3 of 28




Recommended third-party AD5044 Datasheet







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)