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Flash Memory. A25L05P Datasheet

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Flash Memory. A25L05P Datasheet
















A25L05P Memory. Datasheet pdf. Equivalent













Part

A25L05P

Description

(A25LxxP) Serial Flash Memory



Feature


www.DataSheet4U.com A25L20P/A25L10P/A25 L05P Series 2Mbit / 1Mbit / 512Kbit, Lo w Voltage, Serial Flash Memory With 85M Hz SPI Bus Interface Document Title 2Mb it / 1Mbit / 512Kbit, Low Voltage, Seri al Flash Memory With 85MHz SPI Bus Inte rface Revision History Rev. No. 0.0 0.1 1.0 History Initial issue Add transie nt voltage (<20ns) on any pin to ground potential spec. F.
Manufacture

AMIC Technology

Datasheet
Download A25L05P Datasheet


AMIC Technology A25L05P

A25L05P; inal version release Issue Date Februar y 13, 2007 April 24, 2007 August 9, 200 7 Remark Preliminary Final (August, 2 007, Version 1.0) AMIC Technology Corp . A25L20P/A25L10P/A25L05P Series 2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interf ace FEATURES „ 2Mbit / 1Mbit / 512Kbit of Flash Memory „ Flexible Sector Arc hitecture - 25L20P: .


AMIC Technology A25L05P

(4/4/8/16/32)KB/64x3 KB - 25L10P: (4/4/8 /16/32)KB/64x1KB - 25L05P: (4/4/8/16/32 )KB „ Bulk Erase (typical) - 25L20P (2 M) in 6s - A25L10P (1M) in 4s - A25L05P (512K) in 3s „ Sector Erase (512 Kbit ) in 1s (typical) „ Page Program (up t o 256 Bytes) in 3ms (typical) „ 2.7 to 3.6V Single Supply Voltage „ SPI Bus Compatible Serial Interface „ 85MHz Cl ock Rate (maximum) „ Dee.


AMIC Technology A25L05P

p Power-down Mode 1µA (typical) „ Top or Bottom boot block configuration avai lable „ Electronic Signatures - JEDEC Standard Two-Byte Signature A25L20P: (2 012h, Bottom) or (2022h, top) A25L10P: (2011h, Bottom) or (2021h, top) A25L05P : (2010h, Bottom) or (2020h, top) - RES Instruction, One-Byte, Signature, for backward compatibility A25L20P (11h) A2 5L10P (10h) A25L05P (.





Part

A25L05P

Description

(A25LxxP) Serial Flash Memory



Feature


www.DataSheet4U.com A25L20P/A25L10P/A25 L05P Series 2Mbit / 1Mbit / 512Kbit, Lo w Voltage, Serial Flash Memory With 85M Hz SPI Bus Interface Document Title 2Mb it / 1Mbit / 512Kbit, Low Voltage, Seri al Flash Memory With 85MHz SPI Bus Inte rface Revision History Rev. No. 0.0 0.1 1.0 History Initial issue Add transie nt voltage (<20ns) on any pin to ground potential spec. F.
Manufacture

AMIC Technology

Datasheet
Download A25L05P Datasheet




 A25L05P
www.DataSheet4U.com
A25L20P/A25L10P/A25L05P Series
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
Document Title
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No.
0.0
0.1
1.0
History
Initial issue
Add transient voltage (<20ns) on any pin to ground potential spec.
Final version release
Issue Date
February 13, 2007
April 24, 2007
August 9, 2007
Remark
Preliminary
Final
(August, 2007, Version 1.0)
AMIC Technology Corp.




 A25L05P
A25L20P/A25L10P/A25L05P Series
2Mbit / 1Mbit / 512Kbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
FEATURES
„ 2Mbit / 1Mbit / 512Kbit of Flash Memory
„ Flexible Sector Architecture
- 25L20P: (4/4/8/16/32)KB/64x3 KB
- 25L10P: (4/4/8/16/32)KB/64x1KB
- 25L05P: (4/4/8/16/32)KB
„ Bulk Erase (typical)
- 25L20P (2M) in 6s
- A25L10P (1M) in 4s
- A25L05P (512K) in 3s
„ Sector Erase (512 Kbit) in 1s (typical)
„ Page Program (up to 256 Bytes) in 3ms (typical)
„ 2.7 to 3.6V Single Supply Voltage
„ SPI Bus Compatible Serial Interface
„ 85MHz Clock Rate (maximum)
„ Deep Power-down Mode 1µA (typical)
„ Top or Bottom boot block configuration available
„ Electronic Signatures
- JEDEC Standard Two-Byte Signature
A25L20P: (2012h, Bottom) or (2022h, top)
A25L10P: (2011h, Bottom) or (2021h, top)
A25L05P: (2010h, Bottom) or (2020h, top)
- RES Instruction, One-Byte, Signature, for backward
compatibility
A25L20P (11h)
A25L10P (10h)
A25L05P (05h)
„ Package options
- 8-pin SOP (150mil or 209mil), 8-pin DIP (300mil) or 8-pin
QFN
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L20P/A25L10P/A25L05P are 2M/1M/512 bit Serial
Flash Memory, with advanced write protection mechanisms,
accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using
the Page Program instruction.
The memory is organized as 4/2/1 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole memory
can be viewed as consisting of 1024/512/256 pages, or 262,144
/131,072/65,536 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Pin Configurations
„ SO8 Connections
„ DIP8 Connections
„ QFN8 Connections
A25L20P/
A25L10P/
A25L05P
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25L20P/
A25L10P/
A25L05P
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
A25L20P/
A25L10P/
A25L05P
S1
DO 2
W3
VSS 4
8 VCC
7 HOLD
6C
5 DIO
(August, 2007, Version 1.0)
1 AMIC Technology Corp.




 A25L05P
Block Diagram
HOLD
W
S
C
DIO
DO
Control Logic
Address register
and Counter
A25L20P/A25L10P/A25L05P Series
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
3FFFh (2M),
1FFFh (1M),
FFFh (512K)
Status
Register
Size of the
read-only
memory area
00000h
000FFh
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
C
Description
Serial Clock
DIO Serial Data Input 1
DO Serial Data Output 2
S Chip Select
W Write Protect
HOLD
Hold
VCC Supply Voltage
VSS Ground
Notes:
1. The DIO is also used as an output pin when the Fast
Read Dual Output instruction and the Fast Read Dual
Input-Output instruction are executed.
2. The DO is also used as an input pin when the Fast
Read Dual Input-Output instruction is executed.
Logic Symbol
VCC
DIO
C
S
W
HOLD
A25L20P/
A25L10P/
A25L05P
DO
VSS
(August, 2007, Version 1.0)
2 AMIC Technology Corp.




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