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Flash Memory. A25L40P Datasheet

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Flash Memory. A25L40P Datasheet
















A25L40P Memory. Datasheet pdf. Equivalent













Part

A25L40P

Description

Serial Flash Memory



Feature


www.DataSheet4U.com A25L40P Series 4 Mb it, Low Voltage, Serial Flash Memory Pr eliminary Document Title 4 Mbit, Low Vo ltage, Serial Flash Memory With 85MHz S PI Bus Interface Revision History Rev. No. 0.0 0.1 0.2 0.3 With 85MHz SPI Bus Interface History Initial issue Add t he Fast Read Dual Operation Instruction Add QFN 8L (5 x 6mm) package type Add QFN 8L (5 x 6mm) p.
Manufacture

AMIC Technology

Datasheet
Download A25L40P Datasheet


AMIC Technology A25L40P

A25L40P; ackage outline dimensions Modify the Par t No. for Top/Bottom boot sector type A dd DIP 8(300mil) package type Modify th e maximum clock rate to 75MHz Issue Da te August 29, 2006 April 4, 2006 April 20, 2006 September 5, 2006 Remark Prel iminary 0.4 Add transient voltage (<2 0ns) on any pin to ground potential spe c. Add the maximum clock rate of 3.0V~3 .6V : 85MHz May 2.


AMIC Technology A25L40P

5, 2007 PRELIMINARY (May, 2007, Versio n 0.4) AMIC Technology Corp. A25L40P Series 4 Mbit, Low Voltage, Serial Flas h Memory Preliminary FEATURES 4 Mbit of Flash Memory Flexible Sector Architect ure (4/4/8/16/32)KB/64x7 KB Bulk Erase (4 Mbit) in 6s (typical) Sector Erase ( 512 Kbit) in 1s (typical) Page Program (up to 256 Bytes) in 3ms (typical) 2.7 to 3.6V Single Sup.


AMIC Technology A25L40P

ply Voltage SPI Bus Compatible Serial In terface 85MHz Clock Rate (maximum) Deep Power-down Mode 1µA (typical) Top or Bottom boot block configuration availab le Electronic Signatures - JEDEC Standa rd two-Byte Signature (2013h) - RES Ins truction, One-Byte, Signature (12h), fo r backward compatibility „ Package opt ions - 8-pin SOP (150mil or 209mil), 16 -pin SOP, 8-pin DIP .





Part

A25L40P

Description

Serial Flash Memory



Feature


www.DataSheet4U.com A25L40P Series 4 Mb it, Low Voltage, Serial Flash Memory Pr eliminary Document Title 4 Mbit, Low Vo ltage, Serial Flash Memory With 85MHz S PI Bus Interface Revision History Rev. No. 0.0 0.1 0.2 0.3 With 85MHz SPI Bus Interface History Initial issue Add t he Fast Read Dual Operation Instruction Add QFN 8L (5 x 6mm) package type Add QFN 8L (5 x 6mm) p.
Manufacture

AMIC Technology

Datasheet
Download A25L40P Datasheet




 A25L40P
www.DataSheet4U.com
A25L40P Series
Preliminary
4 Mbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
Document Title
4 Mbit, Low Voltage, Serial Flash Memory With 85MHz SPI Bus Interface
Revision History
Rev. No.
0.0
0.1
0.2
0.3
0.4
History
Initial issue
Add the Fast Read Dual Operation Instruction
Add QFN 8L (5 x 6mm) package type
Add QFN 8L (5 x 6mm) package outline dimensions
Modify the Part No. for Top/Bottom boot sector type
Add DIP 8(300mil) package type
Modify the maximum clock rate to 75MHz
Add transient voltage (<20ns) on any pin to ground potential spec.
Add the maximum clock rate of 3.0V~3.6V : 85MHz
Issue Date
August 29, 2006
April 4, 2006
April 20, 2006
September 5, 2006
May 25, 2007
Remark
Preliminary
PRELIMINARY (May, 2007, Version 0.4)
AMIC Technology Corp.




 A25L40P
A25L40P Series
Preliminary
4 Mbit, Low Voltage, Serial Flash Memory
With 85MHz SPI Bus Interface
FEATURES
„ 4 Mbit of Flash Memory
„ Flexible Sector Architecture (4/4/8/16/32)KB/64x7 KB
„ Bulk Erase (4 Mbit) in 6s (typical)
„ Sector Erase (512 Kbit) in 1s (typical)
„ Page Program (up to 256 Bytes) in 3ms (typical)
„ 2.7 to 3.6V Single Supply Voltage
„ SPI Bus Compatible Serial Interface
„ 85MHz Clock Rate (maximum)
„ Deep Power-down Mode 1µA (typical)
„ Top or Bottom boot block configuration available
„ Electronic Signatures
- JEDEC Standard two-Byte Signature (2013h)
- RES Instruction, One-Byte, Signature (12h), for backward
compatibility
„ Package options
- 8-pin SOP (150mil or 209mil), 16-pin SOP, 8-pin DIP
(300mil) or 8-pin QFN
- All Pb-free (Lead-free) products are RoHS compliant
GENERAL DESCRIPTION
The A25L40P is a 4 Mbit (512K x 8) Serial Flash Memory, with
advanced write protection mechanisms, accessed by a high
speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using
the Page Program instruction.
The memory is organized as 8 sectors, each containing 256
pages. Each page is 256 bytes wide. Thus, the whole memory
can be viewed as consisting of 2048 pages, or 524,288 bytes.
The whole memory can be erased using the Bulk Erase
instruction, or a sector at a time, using the Sector Erase
instruction.
Pin Configurations
„ SO8 Connections
„ SO16 Connections
A25L40P
S1
Q2
W3
VSS 4
8 VCC
7 HOLD
6C
5D
A25L40P
HOLD 1 16 C
VCC 2 15 D
DU 3 14 DU
DU 4 13 DU
DU 5 12 DU
DU 6 11 DU
S 7 10 VSS
Q8 9 W
„ DIP8 Connections
Note:
DU = Do not Use
„ QFN8 Connections
A25L40P
S1
Q2
W3
VSS 4
8 VCC
7 HOLD
6C
5D
A25L40P
S1
Q2
W3
VSS 4
8 VCC
7 HOLD
6C
5D
PRELIMINARY (May, 2007, Version 0.4)
1
AMIC Technology Corp.




 A25L40P
Block Diagram
HOLD
W
S
C
D
Q
Control Logic
Address register
and Counter
A25L40P Series
High Voltage
Generator
I/O Shift Register
256 Byte
Data Buffer
7FFFFh
Status
Register
Size of the
read-only
memory area
00000h
000FFh
256 Byte (Page Size)
X Decoder
Pin Descriptions
Pin No.
C
D
Q
S
W
HOLD
VCC
VSS
Description
Serial Clock
Serial Data Input
Serial Data Output
Chip Select
Write Protect
Hold
Supply Voltage
Ground
Logic Symbol
VCC
D
C
S
W
HOLD
Q
A25L40P
VSS
PRELIMINARY (May, 2007, Version 0.4)
2
AMIC Technology Corp.




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