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MX29F001TPC. 29F001TPC Datasheet

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MX29F001TPC. 29F001TPC Datasheet
















29F001TPC MX29F001TPC. Datasheet pdf. Equivalent













Part

29F001TPC

Description

MX29F001TPC



Feature


www.DataSheet4U.com MX29F001T/B 1M-BIT [128K x 8] CMOS FLASH MEMORY FEATURES 5 .0V ± 10% for read, erase and write op eration 131072x8 only organization Fast access time: 90/120ns Low power consum ption - 30mA maximum active current(5MH z) - 1uA typical standby current • Co mmand register architecture - Byte Prog ramming (7us typical) - Sector Erase (8 K-Byte x 1, 4K-Byte x.
Manufacture

Macronix International

Datasheet
Download 29F001TPC Datasheet


Macronix International 29F001TPC

29F001TPC; 2, 8K Byte x 2, 32K-Byte x 1, and 64K-B yte x 1) • Auto Erase (chip & sector) and Auto Program - Automatically erase any combination of sectors with Erase Suspend capability. - Automatically pro grams and verifies data at specified ad dress • Erase Suspend/Erase Resume Suspends an erase operation to read d ata from, or program data to, a sector that is not being erased.


Macronix International 29F001TPC

, then resumes the erase operation. • • • • • Status Reply - Data pol ling & Toggle bit for detection of prog ram and erase cycle completion. • Chi p protect/unprotect for 5V only system or 5V/12V system • 100,000 minimum er ase/program cycles • Latch-up protect ed to 100mA from -1 to VCC+1V • Boot Code Sector Architecture - T = Top Boot Sector - B = Bottom Boot Sector • L.


Macronix International 29F001TPC

ow VCC write inhibit is equal to or less than 3.2V • Package type: - 32-pin P LCC - 32-pin TSOP - 32-pin PDIP • Boo t Code Sector Architecture - T=Top Boot Sector - B=Bottom Boot Sector • 20 y ears data retention GENERAL DESCRIPTIO N The MX29F001T/B is a 1-mega bit Flash memory organized as 128K bytes of 8 bi ts only MXIC's Flash memories offer the most cost-effective and.





Part

29F001TPC

Description

MX29F001TPC



Feature


www.DataSheet4U.com MX29F001T/B 1M-BIT [128K x 8] CMOS FLASH MEMORY FEATURES 5 .0V ± 10% for read, erase and write op eration 131072x8 only organization Fast access time: 90/120ns Low power consum ption - 30mA maximum active current(5MH z) - 1uA typical standby current • Co mmand register architecture - Byte Prog ramming (7us typical) - Sector Erase (8 K-Byte x 1, 4K-Byte x.
Manufacture

Macronix International

Datasheet
Download 29F001TPC Datasheet




 29F001TPC
www.DataSheet4U.com
MX29F001T/B
1M-BIT [128K x 8] CMOS FLASH MEMORY
FEATURES
• 5.0V ± 10% for read, erase and write operation
• 131072x8 only organization
• Fast access time: 90/120ns
• Low power consumption
- 30mA maximum active current(5MHz)
- 1uA typical standby current
• Command register architecture
- Byte Programming (7us typical)
- Sector Erase (8K-Byte x 1, 4K-Byte x 2, 8K Byte
x 2, 32K-Byte x 1, and 64K-Byte x 1)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors
with Erase Suspend capability.
- Automatically programs and verifies data at
specified address
• Erase Suspend/Erase Resume
– Suspends an erase operation to read data from,
or program data to, a sector that is not being
erased, then resumes the erase operation.
• Status Reply
- Data polling & Toggle bit for detection of program
and erase cycle completion.
• Chip protect/unprotect for 5V only system or 5V/12V
system
• 100,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1 to VCC+1V
• Boot Code Sector Architecture
- T = Top Boot Sector
- B = Bottom Boot Sector
• Low VCC write inhibit is equal to or less than 3.2V
• Package type:
- 32-pin PLCC
- 32-pin TSOP
- 32-pin PDIP
• Boot Code Sector Architecture
- T=Top Boot Sector
- B=Bottom Boot Sector
• 20 years data retention
GENERAL DESCRIPTION
The MX29F001T/B is a 1-mega bit Flash memory
organized as 128K bytes of 8 bits only MXIC's
Flash memories offer the most cost-effective and
reliable read/write non-volatile random access
memory. The MX29F001T/B is packaged in 32-pin
PLCC, TSOP, PDIP. It is designed to be repro-
grammed and erased in-system or in-standard
EPROM programmers.
The standard MX29F001T/B offers access time
90ns. To eliminate bus contention, the MX29F001T/
B has separate chip enable (CE) and output enable
(OE) controls.
MXIC's Flash memories augment EPROM function-
ality with in-circuit electrical erasure and
programming. The MX29F001T/B uses a command
register to manage this functionality. The command
register allows for 100% TTL level control inputs
and fixed power supply levels during erase and
programming, while maintaining maximum EPROM
compatibility.
MXIC Flash technology reliably stores memory con-
tents even after 100,000 erase and program cycles.
The MXIC cell is designed to optimize the erase and
programming mechanisms. In addition, the combi-
nation of advanced tunnel oxide processing and low
internal electric fields for erase and programming
operations produces reliable cycling. The
MX29F001T/B uses a 5.0V ± 10% VCC supply to
perform the High Reliability Erase and auto
Program/Erase algorithms.
The highest degree of latch-up protection is
achieved with MXIC's proprietary non-epi process.
Latch-up protection is proved for stresses up to 100
milliamps on address and data pin from -1V to VCC
+ 1V.
P/N: PM0515
REV. 2.6, DEC. 29, 2003
1




 29F001TPC
www.DataSheet4U.com
MX29F001T/B
PIN CONFIGURATIONS
32 PDIP
NC
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VCC
31 WE
30 NC
29 A14
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CE
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
32 TSOP (TYPE 1)
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
MX29F001T/B
(NORMAL TYPE)
32 PLCC
4
A7 5
1 32
30
29 A14
A6 A13
A5 A8
A4 A9
A3 9 MX29F001T/B 25 A11
A2 OE
A1 A10
A0 CE
Q0 13
14
21 Q7
17 20
PIN DESCRIPTION:
32 OE
31 A10
30 CE
29 Q7
28 Q6
27 Q5
26 Q4
25 Q3
24 GND
23 Q2
22 Q1
21 Q0
20 A0
19 A1
18 A2
17 A3
SYMBOL
A0~A16
Q0~Q7
CE
WE
OE
VCC
GND
PIN NAME
Address Input
Data Input/Output
Chip Enable Input
Write Enable Input
Output Enable Input
Power Supply Pin (+5V)
Ground Pin
SECTOR STRUCTURE
A16~A0
1FFFFH
1DFFFH
1CFFFH
1BFFFH
19FFFH
17FFFH
0FFFFH
00000H
8 K-BYTE
4 K-BYTE
4 K-BYTE
8 K-BYTE
8 K-BYTE
32 K-BYTE
64 K-BYTE
MX29F001T Sector Architecture
P/N: PM0515
A16~A0
1FFFFH
0FFFFH
07FFFH
05FFFH
03FFFH
02FFFH
01FFFH
00000H
64 K-BYTE
32 K-BYTE
8 K-BYTE
8 K-BYTE
4 K-BYTE
4 K-BYTE
8 K-BYTE
MX29F001B Sector Architecture
REV. 2.6, DEC. 29, 2003
2




 29F001TPC
www.DataSheet4U.com
BLOCK DIAGRAM
MX29F001T/B
CONTROL
CE
OE INPUT
WE LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
A0-A16
ADDRESS
LATCH
AND
BUFFER
Q0-Q7
MX29F001T/B
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
SENSE PGM
AMPLIFIER DATA
HV
PROGRAM
DATA LATCH
STATE
REGISTER
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
P/N: PM0515
REV. 2.6, DEC. 29, 2003
3




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