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PHP50N03LT. 50N03LT Datasheet

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PHP50N03LT. 50N03LT Datasheet






50N03LT PHP50N03LT. Datasheet pdf. Equivalent




50N03LT PHP50N03LT. Datasheet pdf. Equivalent





Part

50N03LT

Description

PHP50N03LT



Feature


Philips Semiconductors Product specific ation N-channel TrenchMOS™ transisto r Logic level FET FEATURES • ’Trenc h’ technology • Very low on-state r esistance • Fast switching • High t hermal cycling performance www.DataShee t4U.com • Low thermal resistance • Logic level compatible PHP50N03LT, PHB 50N03LT PHD50N03LT QUICK REFERENCE DATA d SYMBOL VDSS = 25 V ID = 48 A RD.
Manufacture

NXP Semiconductors

Datasheet
Download 50N03LT Datasheet


NXP Semiconductors 50N03LT

50N03LT; S(ON) ≤ 16 mΩ (VGS = 10 V) RDS(ON) 21 mΩ (VGS = 5 V) g s GENERAL D ESCRIPTION N-channel enhancement mode l ogic level field-effect power transisto r in a plastic envelope using ’trench ’ technology. Applications:• High f requency computer motherboard d.c. to d .c. converters • High current switchi ng The PHP50N03LT is supplied in the SO T78 (TO220AB) conventional leaded .


NXP Semiconductors 50N03LT

package. The PHB50N03LT is supplied in t he SOT404 (D2PAK) surface mounting pack age. The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package. PINNING PIN 1 2 3 tab DESCRIPTION gate drain 1 source SOT78 (TO220AB) tab S OT404 (D2PAK) tab SOT428 (DPAK) tab 2 1 23 2 1 3 1 3 drain LIMITING V ALUES Limiting values in accordance wit h the Absolute Max.


NXP Semiconductors 50N03LT

imum System (IEC 134) SYMBOL PARAMETER V DSS VDGR VGS VGSM ID IDM Ptot Tj, Tstg Drain-source voltage Drain-gate voltage Gate-source voltage (DC) Gate-source v oltage (pulse peak value) Drain current (DC) Drain current (pulse peak value) Total power dissipation Operating junct ion and storage temperature CONDITIONS Tj = 25 ˚C to 175˚C Tj = 25 ˚C to 17 5˚C; RGS = 20 kΩ Tj ≤.

Part

50N03LT

Description

PHP50N03LT



Feature


Philips Semiconductors Product specific ation N-channel TrenchMOS™ transisto r Logic level FET FEATURES • ’Trenc h’ technology • Very low on-state r esistance • Fast switching • High t hermal cycling performance www.DataShee t4U.com • Low thermal resistance • Logic level compatible PHP50N03LT, PHB 50N03LT PHD50N03LT QUICK REFERENCE DATA d SYMBOL VDSS = 25 V ID = 48 A RD.
Manufacture

NXP Semiconductors

Datasheet
Download 50N03LT Datasheet




 50N03LT
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP50N03LT, PHB50N03LT
PHD50N03LT
FEATURES
’Trench’ technology
• Very low on-state resistance
• Fast switching
www.DataSheetH4Uig.chomthermal cycling performance
• Low thermal resistance
• Logic level compatible
SYMBOL
g
d
s
QUICK REFERENCE DATA
VDSS = 25 V
ID = 48 A
RDS(ON) 16 m(VGS = 10 V)
RDS(ON) 21 m(VGS = 5 V)
GENERAL DESCRIPTION
N-channel enhancement mode logic level field-effect power transistor in a plastic envelope using ’trench’ technology.
Applications:-
• High frequency computer motherboard d.c. to d.c. converters
• High current switching
The PHP50N03LT is supplied in the SOT78 (TO220AB) conventional leaded package.
The PHB50N03LT is supplied in the SOT404 (D2PAK) surface mounting package.
The PHD50N03LT is supplied in the SOT428 (DPAK)surface mounting package.
PINNING
SOT78 (TO220AB) SOT404 (D2PAK)
PIN DESCRIPTION
1 gate
tab
tab
SOT428 (DPAK)
tab
2 drain 1
3 source
tab drain
1 23
2
13
2
13
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134)
SYMBOL PARAMETER
CONDITIONS
VDSS
VDGR
VGS
VGSM
ID
IDM
Ptot
Tj, Tstg
Drain-source voltage
Drain-gate voltage
Gate-source voltage (DC)
Gate-source voltage (pulse
peak value)
Drain current (DC)
Drain current (pulse peak
value)
Total power dissipation
Operating junction and
storage temperature
Tj = 25 ˚C to 175˚C
Tj = 25 ˚C to 175˚C; RGS = 20 k
Tj 150˚C
Tmb = 25 ˚C
Tmb = 100 ˚C
Tmb = 25 ˚C
Tmb = 25 ˚C
MIN.
-
-
-
-
-
-
-
-
- 55
MAX.
25
25
± 15
± 20
48
34
180
86
175
UNIT
V
V
V
V
A
A
A
W
˚C
1 It is not possible to make connection to pin:2 of the SOT404 or SOT428 packages.
October 1999
1
Rev 1.800




 50N03LT
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP50N03LT, PHB50N03LT
PHD50N03LT
THERMAL RESISTANCES
SYMBOL PARAMETER
Rth j-mb
www.DataSheetR4Uth.jc-aom
Thermal resistance junction
to mounting base
Thermal resistance junction
to ambient
CONDITIONS
SOT78 package, in free air
SOT404 and SOT428 packages, pcb
mounted, minimum footprint
MIN. TYP. MAX. UNIT
- - 1.75 K/W
- 60 - K/W
- 50 - K/W
AVALANCHE LIMITING VALUE
SYMBOL PARAMETER
CONDITIONS
WDSS
Drain-source non-repetitive ID = 25 A; VDD 15 V;
unclamped inductive turn-off VGS = 5 V; RGS = 50 ; Tmb = 25 ˚C
energy
MIN.
-
MAX.
60
UNIT
mJ
ELECTRICAL CHARACTERISTICS
Tj= 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
V(BR)DSS
VGS(TO)
RDS(ON)
gfs
IDSS
IGSS
Qg(tot)
Qgs
Qgd
td on
tr
td off
tf
Ld
Ld
Ls
Drain-source breakdown
voltage
Gate threshold voltage
Drain-source on-state
resistance
Forward transconductance
Zero gate voltage drain
current
Gate source leakage current
Total gate charge
Gate-source charge
Gate-drain (Miller) charge
VGS = 0 V; ID = 0.25 mA;
Tj = -55˚C
VDS = VGS; ID = 1 mA
Tj = 175˚C
Tj = -55˚C
VGS = 10 V; ID = 25 A
VGS = 10 V; ID = 25 A (SOT428 package)
VGS = 5 V; ID = 25 A
VGS = 5 V; ID = 25 A; Tj = 175˚C
VDS = 25 V; ID = 25 A
VDS = 25 V; VGS = 0 V;
Tj = 175˚C
VGS = ±5 V; VDS = 0 V
ID = 50 A; VDD = 15 V; VGS = 5 V
Turn-on delay time
Turn-on rise time
Turn-off delay time
Turn-off fall time
VDD = 15 V; ID = 25 A;
VGS = 10 V; RG = 5
Resistive load
Internal drain inductance
Internal drain inductance
Internal source inductance
Measured tab to centre of die
Measured from drain lead to centre of die
(SOT78 package only)
Measured from source lead to source
bond pad
Ciss Input capacitance
Coss Output capacitance
Crss Feedback capacitance
VGS = 0 V; VDS = 25 V; f = 1 MHz
MIN. TYP. MAX. UNIT
25 -
-V
22 -
-V
1 1.5 2
V
0.5 -
-V
- - 2.3 V
- 13 16 m
- 15 18 m
- 18 21 m
- - 39 m
8 27 - S
- 0.05 10 µA
- - 500 µA
- 10 100 nA
- 17 - nC
- 7.6 - nC
- 11 - nC
- 6.4 12 ns
- 62 75 ns
- 50 75 ns
- 30 45 ns
- 3.5 - nH
- 4.5 - nH
- 7.5 - nH
- 1050 -
- 330 -
- 220 -
pF
pF
pF
October 1999
2
Rev 1.800




 50N03LT
Philips Semiconductors
N-channel TrenchMOStransistor
Logic level FET
Product specification
PHP50N03LT, PHB50N03LT
PHD50N03LT
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25˚C unless otherwise specified
SYMBOL PARAMETER
CONDITIONS
www.DataSheetI4SU.com
ISM
VSD
trr
Qrr
Continuous source current
(body diode)
Pulsed source current (body
diode)
Diode forward voltage
Reverse recovery time
Reverse recovery charge
IF = 25 A; VGS = 0 V
IF = 40 A; VGS = 0 V
IF = 20 A; -dIF/dt = 100 A/µs;
VGS = 0 V; VR = 25 V
MIN. TYP. MAX. UNIT
- - 48 A
- - 180 A
- 0.95 1.2 V
- 1.05 -
- 100 -
- 0.13 -
ns
µC
Normalised Power Derating, PD (%)
100
90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125 150
Mounting Base temperature, Tmb (C)
Fig.1. Normalised power dissipation.
PD% = 100PD/PD 25 ˚C = f(Tmb)
175
Normalised Current Derating, ID (%)
100
90
80
70
60
50
40
30
20
10
0
0 25 50 75 100 125
Mounting Base temperature, Tmb (C)
150
175
Fig.2. Normalised continuous drain current.
ID% = 100ID/ID 25 ˚C = f(Tmb); conditions: VGS 5 V
1000 Peak Pulsed Drain Current, IDM (A)
RDS(on) = VDS/ ID
100
10
D.C.
tp = 10 us
100 us
1 ms
10 ms
100 ms
1
1 10 100
Drain-Source Voltage, VDS (V)
Fig.3. Safe operating area
ID & IDM = f(VDS); IDM single pulse; parameter tp
Transient thermal impedance, Zth j-mb (K/W)
10
D = 0.5
1
0.2
0.1
0.05
0.1
0.02
P
D
D = tp/T
tp
single pulse
0.01
1E-06
1E-05
T
1E-04
1E-03
1E-02
Pulse width, tp (s)
1E-01
1E+00
Fig.4. Transient thermal impedance.
Zth j-mb = f(t); parameter D = tp/T
October 1999
3
Rev 1.800






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