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FTG. CY28349 Datasheet

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FTG. CY28349 Datasheet
















CY28349 FTG. Datasheet pdf. Equivalent













Part

CY28349

Description

FTG



Feature


CY28349 FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan & CK-408 Clock Synthe sizer/Driver Specifications • System frequency synthesizer for Intel Brookda le 845 and Brookdale - G Pentium® 4 Ch ipsets www.DataSheet4U.com • Programm able clock output frequency with less t han 1 MHz increment • Integrated fail -safe Watchdog timer for syste.
Manufacture

SpectraLinear

Datasheet
Download CY28349 Datasheet


SpectraLinear CY28349

CY28349; m recovery • Automatically switch to H W selected or SW programmed clock frequ ency when watchdog timer time-out • F ixed 3V66 and PCI output frequency mode • Capable of generating system RESET after a Watchdog timer time-out occurs or a change in output frequency via SM Bus interface • Support SMBus byte re ad/write and block read/ write operatio ns to simplify system BIOS.


SpectraLinear CY28349

development • Vendor ID and Revision ID support • Programmable drive stren gth support • Programmable output ske w support • Power management control inputs • Available in 48-pin SSOP CPU x3 3V66 x4 PCI x 10 REF x2 48M x1 24_4 8M x1 Block Diagram X1 X2 Pin Configu ration [1] VDD_REF REF0:1 XTAL OSC PLL 1 PLL Ref Freq Divider Network *FS0: 4 VTT_PWRGD# *MULTSEL0:1 PW.


SpectraLinear CY28349

R_DWN# PLL2 2 SDATA SCLK SMBus Logic *MULTSEL1/REF1 VDD_REF X1 X2 GND_PCI *FS2/PCI_F0 *FS3/PCI_F1 PCI_F2 VDD_PCI VDD_3V66 *FS4/PCI0 3V66_0:2 PCI1 PCI2 G ND_PCI VDD_PCI PCI3 PCI_F0:2 PCI4 PCI0: 6 PCI5 VDD_48MHz PCI6 3V66_3/48MHz_1 VD D_PCI VTT_PWRGD# VDD_48MHz 48MHz_0 RST# GND_48MHz *FS0/48MHz_0 24_48MHz *FS1/2 4_48MHz VDD_48MHz VDD_CPU CPU0:1, CPU0: 1#, CPU_ITP, CPU_I.





Part

CY28349

Description

FTG



Feature


CY28349 FTG for Intel® Pentium® 4 CPU and Chipsets Features • Compatible to Intel® CK-Titan & CK-408 Clock Synthe sizer/Driver Specifications • System frequency synthesizer for Intel Brookda le 845 and Brookdale - G Pentium® 4 Ch ipsets www.DataSheet4U.com • Programm able clock output frequency with less t han 1 MHz increment • Integrated fail -safe Watchdog timer for syste.
Manufacture

SpectraLinear

Datasheet
Download CY28349 Datasheet




 CY28349
CY28349
FTG for Intel® Pentium® 4 CPU and Chipsets
Features
• Compatible to Intel® CK-Titan & CK-408 Clock Synthe-
sizer/Driver Specifications
• System frequency synthesizer for Intel Brookdale 845
www.DataSheeta4nUd.coBmrookdale - G Pentium® 4 Chipsets
• Programmable clock output frequency with less than
1 MHz increment
• Integrated fail-safe Watchdog timer for system
recovery
• Automatically switch to HW selected or SW
programmed clock frequency when watchdog timer
time-out
• Fixed 3V66 and PCI output frequency mode
• Capable of generating system RESET after a Watchdog
timer time-out occurs or a change in output frequency
via SMBus interface
• Support SMBus byte read/write and block read/ write
operations to simplify system BIOS development
• Vendor ID and Revision ID support
• Programmable drive strength support
• Programmable output skew support
• Power management control inputs
• Available in 48-pin SSOP
CPU
3V66
PCI
REF
48M
24_48M
x 3 x 4 x 10 x 2 x 1 x 1
Block Diagram
X1
X2
*FS0:4
VTT_PWRGD#
*MULTSEL0:1
XTAL
OSC
PLL Ref Freq
PLL 1
Divider
Network
PWR_DWN#
PLL2
SDATA
SCLK
SMBus
Logic
2
VDD_REF
REF0:1
Pin Configuration [1]
*MULTSEL1/REF1
VDD_CPU
CPU0:1, CPU0:1#,
VDD_REF
CPU_ITP, CPU_ITP#
X1
X2
GND_PCI
*FS2/PCI_F0
*FS3/PCI_F1
PCI_F2
VDD_PCI
VDD_3V66
*FS4/PCI0
3V66_0:2
PCI1
PCI2
VDD_PCI
PCI_F0:2
GND_PCI
PCI3
PCI4
PCI0:6
VDD_48MHz
3V66_3/48MHz_1
PCI5
PCI6
VDD_PCI
VDD_48MHz
VTT_PWRGD#
48MHz_0
RST#
GND_48MHz
24_48MHz
*FS0/48MHz_0
*FS1/24_48MHz
VDD_48MHz
RST#
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 38
12 37
13 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
SSOP-48
REF0/MULTSEL0*
GND_REF
VDD_CPU
CPU_ITP
CPU_ITP#
GND_CPU
PWR_DWN#
CPU0
CPU0#
VDD_CPU
CPU1
CPU1#
GND_CPU
IREF
VDD_CORE
GND_CORE
VDD_3V66
3V66_0
3V66_1
GND_3V66
3V66_2
3V66_3/48MHz_1
SCLK
SDATA
Note:
1. Signals marked with ‘*’ and “^” have internal pull-up and pull-down resistors respectively.
Rev 1.0, November 24, 2006
2200 Laurelwood Road, Santa Clara, CA 95054
Tel:(408) 855-0555 Fax:(408) 855-0550
Page 1 of 20
www.SpectraLinear.com




 CY28349
CY28349
Pin Definitions
Pin Name
X1
X2
REF0/MULTSEL0
www.DataSheet4U.com
REF1/MULTSEL1
CPU0:1, CPU0:1#
CPU_ITP,
CPU_ITP#
3V66_0:2
PCI_F0/FS2
PCI_F1/FS3
PCI_F2
PCI0/FS4
PCI1:6
48MHz_0/FS0
24_48MHz/FS1
3V66_3/48MHz_1
Pin No.
3
4
48
1
41, 38, 40,
37
44, 45
31, 30, 28
6
7
8
10
11, 12, 14,
15, 16, 17
22
23
27
Pin
Type
I
O
I/O
I/O
O
I/O
O
I/O
I/O
I/O
I/O
O
Pin Description
Crystal Connection or External Reference Frequency Input: This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
Crystal Connection: Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
Reference Clock 0/Current Multiplier Selection 0: 3.3V 14.318-MHz clock
output. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
Reference Clock 1/Current Multiplier Selection 1: 3.3V 14.318-MHz clock
output. This pin also serves as a power-on strap option to determine the current
multiplier for the CPU clock outputs. The MULTSEL1:0 definitions are as follows:
MULTSEL1:0
00 = Ioh is 4 x IREF
01 = Ioh is 5 x IREF
10 = Ioh is 6 x IREF
11 = Ioh is 7 x IREF
CPU Clock Outputs: Frequency is set by the FS0:4 inputs or through serial input
interface.
CPU Clock Output for ITP: Frequency is set by the FS0:4 inputs or through
serial input interface.
66 MHz Clock Outputs: 3.3V fixed 66-MHz clock.
Free-running PCI Output 0/Frequency Select 2: 3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine device operating
frequency as described in the Frequency Selection Table.
Free-running PCI Output 1/Frequency Select 3: 3.3V free-running PCI output.
This pin also serves as a power-on strap option to determine device operating
frequency as described in Table 4.
Free-running PCI Output 2: 3.3V free-running PCI output.
PCI Output 0/Frequency Select 4: 3.3V PCI output. This pin also serves as a
power-on strap option to determine device operating frequency as described in
Table 4.
PCI Clock Output 1 to 6: 3.3V PCI clock outputs.
I/O 48 MHz Output/Frequency Select 0: 3.3V fixed 48-MHz, non-spread spectrum
output. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 4.
This output will be used as the reference clock for USB host controller in Intel 845
(Brookdale) platforms. For Intel Brookdale - G platforms, this output will be used
as the VCH reference clock.
I/O 24 or 48MHz Output/Frequency Select 1: 3.3V fixed 24 MHz or 48 MHz
non-spread spectrum output. This pin also serves as a power-on strap option to
determine device operating frequency as described in Table 4.
This output will be used as the reference clock for SIO devices in Intel® 845
(Brookdale) platforms. For Intel® Brookdale - G platforms, this output will be used
as the reference clock for both USB host controller and SIO devices. We
recommend system designer to configure this output as 48 MHz and “HIGH
Drive” by setting Byte [5], Bit [0] and Byte [9], Bit [7], respectively.
O 48 MHz or 66 MHz Output: 3.3V output.
Rev 1.0, November 24, 2006
Page 2 of 20




 CY28349
CY28349
Pin Definitions (continued)
Pin Name
PWR_DWN#
Pin No.
42
SCLK
SDATA
RST#
26
25
20
www.DataSheeIRt4EUF.com
VTT_PWRGD#
35
19
VDD_REF,
VDD _PCI,
VDD_48MHz,
VDD_3V66,
VDD_CPU
GND_PCI,
GND_48MHz,
GND_3V66,
GND_CPU,
GND_REF,
VDD_CORE
GND_CORE
2, 9, 18, 24,
32, 39, 46
5, 13, 21, 29,
36, 43, 47
34
33
Pin
Type
I
I
I/O
O
(open-
drain)
I
I
P
G
P
G
Pin Description
Power Down Control: 3.3V LVTTL compatible input that places the device in
power down mode when held low.
SMBus Clock Input: Clock pin for serial interface.
SMBus Data Input: Data pin for serial interface.
System Reset Output: Open-drain system reset output.
Current Reference for CPU output: A precision resistor is attached to this pin
which is connected to the internal current reference.
Powergood from Voltage Regulator Module (VRM): 3.3V LVTTL input.
VTT_PWRGD# is a level-sensitive strobe used to determine when FS0:4 and
MULTSEL0:1 inputs are valid and OK to be sampled (Active LOW). Once
VTT_PWRGD# is sampled LOW, the status of this input will be ignored.
3.3V Power Connection: Power supply for CPU outputs buffers, 3V66 output
buffers, PCI output buffers, reference output buffers and 48-MHz output buffers.
Connect to 3.3V.
Ground Connection: Connect all ground pins to the common system ground
plane.
3.3V Analog Power Connection: Power supply for core logic, PLL circuitry.
Connect to 3.3V.
Analog Ground Connection: Ground for core logic, PLL circuitry.
Rev 1.0, November 24, 2006
Page 3 of 20




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