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CMOS E2PROM. CAT28WC129 Datasheet

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CMOS E2PROM. CAT28WC129 Datasheet
















CAT28WC129 E2PROM. Datasheet pdf. Equivalent













Part

CAT28WC129

Description

128K-Bit I2C Serial CMOS E2PROM



Feature


Preliminary CAT24WC129 128K-Bit I2C Ser ial CMOS E2PROM FEATURES s 1MHz I2C Bus Compatible* s 1.8 to 6 Volt Operation s Low Power CMOS Technology s 64-Byte P age Write Buffer s Self-Timed www.DataS heet4U.com s Write Protect Feature – Top 1/4 Array Protected When WP at VIH s 100,000 Program/Erase Cycles s 100 Y ear Data Retention s 8-Pin DIP or 8-Pin SOIC Write Cycle w.
Manufacture

Catalyst Semiconductor

Datasheet
Download CAT28WC129 Datasheet


Catalyst Semiconductor CAT28WC129

CAT28WC129; ith Auto-Clear s Commercial, Industrial and Automotive Temperature Ranges DE SCRIPTION The CAT24WC129 is a 128K-bit Serial CMOS E2PROM internally organized as 16384 words of 8 bits each. Catalys t’s advanced CMOS technology substant ially reduces device power requirements . The CAT24WC129 features a 64-byte pag e write buffer. The device operates via the I2C bus serial .


Catalyst Semiconductor CAT28WC129

interface and is available in 8-pin DIP or 8-pin SOIC packages. PIN CONFIGURAT ION DIP Package (P) NC NC NC VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA BLOCK DIAGRAM EXTERNAL LOAD DOUT ACK SENSE AMPS SHIF T REGISTERS VCC VSS WORD ADDRESS BUFFE RS COLUMN DECODERS 512 SOIC Package ( J,K) NC NC NC VSS 1 2 3 4 8 7 6 5 VCC W P SCL SDA SDA START/STOP LOGIC XDEC WP CONTROL LOGIC .


Catalyst Semiconductor CAT28WC129

256 E2PROM 256X512 24WC129 F01 PIN FU NCTIONS Pin Name SDA SCL WP VCC VSS Fun ction Serial Data/Address Serial Clock Write Protect +1.8V to +6V Power Supply SCL STATE COUNTERS DATA IN STORAGE H IGH VOLTAGE/ TIMING CONTROL Ground 24W C129 F02 * Catalyst Semiconductor is l icensed by Philips Corporation to carry the I2C Bus Protocol. © 1998 by Cata lyst Semiconductor,.





Part

CAT28WC129

Description

128K-Bit I2C Serial CMOS E2PROM



Feature


Preliminary CAT24WC129 128K-Bit I2C Ser ial CMOS E2PROM FEATURES s 1MHz I2C Bus Compatible* s 1.8 to 6 Volt Operation s Low Power CMOS Technology s 64-Byte P age Write Buffer s Self-Timed www.DataS heet4U.com s Write Protect Feature – Top 1/4 Array Protected When WP at VIH s 100,000 Program/Erase Cycles s 100 Y ear Data Retention s 8-Pin DIP or 8-Pin SOIC Write Cycle w.
Manufacture

Catalyst Semiconductor

Datasheet
Download CAT28WC129 Datasheet




 CAT28WC129
Preliminary
CAT24WC129
128K-Bit I2C Serial CMOS E2PROM
FEATURES
s 1MHz I2C Bus Compatible*
s 1.8 to 6 Volt Operation
s Low Power CMOS Technology
s 64-Byte Page Write Buffer
www.DataSheet4sU.cSomelf-Timed Write Cycle with Auto-Clear
s Commercial, Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT24WC129 is a 128K-bit Serial CMOS E2PROM
internally organized as 16384 words of 8 bits each.
Catalyst’s advanced CMOS technology substantially
reduces device power requirements. The
s Write Protect Feature
– Top 1/4 Array Protected When WP at VIH
s 100,000 Program/Erase Cycles
s 100 Year Data Retention
s 8-Pin DIP or 8-Pin SOIC
CAT24WC129 features a 64-byte page write buffer. The
device operates via the I2C bus serial interface and is
available in 8-pin DIP or 8-pin SOIC packages.
PIN CONFIGURATION
DIP Package (P)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
SOIC Package (J,K)
NC
NC
NC
VSS
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
24WC129 F01
PIN FUNCTIONS
Pin Name
Function
SDA
Serial Data/Address
SCL Serial Clock
WP Write Protect
VCC +1.8V to +6V Power Supply
VSS Ground
BLOCK DIAGRAM
EXTERNAL LOAD
VCC
VSS
DOUT
ACK
WORD ADDRESS
BUFFERS
SDA
START/STOP
LOGIC
SENSE AMPS
SHIFT REGISTERS
COLUMN
DECODERS
512
XDEC 256
E2PROM
256X512
CONTROL
WP LOGIC
SCL STATE COUNTERS
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
24WC129 F02
© 1998 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 25065-00 6/99 S-1




 CAT28WC129
CAT24WC129
Preliminary
ABSOLUTE MAXIMUM RATINGS*
*COMMENT
Temperature Under Bias
–55°C to +125°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground(1) ........... –2.0V to +VCC + 2.0V
VCC with Respect to Ground ............... –2.0V to +7.0V
Package Power Dissipation
Capability (Ta = 25°C) ................................... 1.0W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current(2) ........................ 100mA
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
www.DataSheReEt4LUI.cAoBmILITY CHARACTERISTICS
Symbol
NEND(3)
TDR(3)
VZAP(3)
ILTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-up
Min.
100,000
100
2000
100
Max.
D.C. OPERATING CHARACTERISTICS
VCC = +1.8V to +6.0V, unless otherwise specified.
Units
Cycles/Byte
Years
Volts
mA
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Limits
Symbol Parameter
Min. Typ. Max. Units Test Conditions
ICC1 Power Supply Current - Read
ICC2 Power Supply Current - Write
ISB(5) Standby Current
ILI
ILO
VIL
VIH
VOL1
VOL2
Input Leakage Current
Output Leakage Current
Input Low Voltage
–1
Input High Voltage
VCC x 0.7
Output Low Voltage (VCC = +3.0V)
Output Low Voltage (VCC = +1.8V)
1 mA
3 mA
0 µA
3
3
VCC x 0.3
VCC + 0.5
0.4
0.5
µA
µA
V
V
V
V
fSCL = 100 KHz
VCC=5V
fSCL = 100 KHz
VCC=5V
VIN = GND or VCC
VCC=5V
VIN = GND to VCC
VOUT = GND to VCC
IOL = 3.0 mA
IOL = 1.5 mA
CAPACITANCE TA = 25°C, f = 1.0 MHz, VCC = 5V
Symbol
Test
Max.
Units
Conditions
CI/O(3) Input/Output Capacitance (SDA)
8 pF
VI/O = 0V
CIN(3)
Input Capacitance (SCL, WP)
6 pF
VIN = 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to VCC +1V.
(5) Standby current (ISB ) = 0 µA (<900 nA).
Doc. No. 25065-00 6/99 S-1
2




 CAT28WC129
Preliminary
CAT24WC129
A.C. CHARACTERISTICS
VCC = +1.8V to +6V, unless otherwise specified
Output Load is 1 TTL Gate and 100pF
Read & Write Cycle Limits
Symbol Parameter
VCC=1.8V - 6.0V VCC=2.5V - 6.0V VCC=3.0V - 5.5V
Min. Max. Min. Max. Min. Max. Units
FSCL
Clock Frequency
100 400 1000 kHz
tAA SCL Low to SDA Data Out
and ACK Out
0.1 3.5
0.05 0.9
0.05 0.55 µs
tBUF(1)
www.DataSheet4U.com
tHD:STA
Time the Bus Must be Free Before
a New Transmission Can Start
Start Condition Hold Time
4.7
4.0
1.2
0.6
0.5 µs
0.25 µs
tLOW
Clock Low Period
4.7 1.2
0.6 µs
tHIGH
Clock High Period
4.0 0.6
0.4 µs
tSU:STA
Start Condition Setup Time
(for a Repeated Start Condition)
4.0
0.6
0.25 µs
tHD:DAT Data In Hold Time
00
0 ns
tSU:DAT
tR(1)
tF(1)
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
100
1.0
300
100
0.3
300
100
0.3
100
ns
µs
ns
tSU:STO Stop Condition Setup Time
4.7
0.6
0.25 µs
tDH Data Out Hold Time
100 50
50 ns
tWR Write Cycle Time
10 10 10 ms
Power-Up Timing (1)(2)
Symbol
Parameter
Max.
Units
tPUR
tPUW
Power-Up to Read Operation
Power-Up to Write Operation
1 ms
1 ms
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During
the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave
address.
FUNCTIONAL DESCRIPTION
The CAT24WC129 supports the I2C Bus data transmis-
sion protocol. This Inter-Integrated Circuit Bus protocol
defines any device that sends data to the bus to be a
transmitter and any device receiving data to be a re-
ceiver. The transfer is controlled by the Master device
which generates the serial clock and all START and
STOP conditions for bus access. The CAT24WC129
operates as a Slave device. Both the Master device and
Slave device can operate as either transmitter or re-
ceiver, but the Master device controls which mode is
activated.
3 Doc. No. 25065-00 6/99 S-1




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