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buffer/line driver. 74AHC2G126 Datasheet

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buffer/line driver. 74AHC2G126 Datasheet






74AHC2G126 driver. Datasheet pdf. Equivalent




74AHC2G126 driver. Datasheet pdf. Equivalent





Part

74AHC2G126

Description

Dual buffer/line driver



Feature


74AHC2G126; 74AHCT2G126 Dual buffer/lin e driver; 3-state Rev. 7 — 6 May 2013 Product data sheet 1. General descri ption The 74AHC2G126 and 74AHCT2G126 a re high-speed Si-gate CMOS devices. The y provide a dual non-inverting buffer/l ine driver with 3-state output. The 3-s tate output is controlled by the output enable input (nOE). A LOW at nOE cause s the output to assu.
Manufacture

NXP Semiconductors

Datasheet
Download 74AHC2G126 Datasheet


NXP Semiconductors 74AHC2G126

74AHC2G126; me a high-impedance OFF-state. The AHC d evice has CMOS input switching levels a nd supply voltage range 2 V to 5.5 V. T he AHCT device has TTL input switching levels and supply voltage range 4.5 V t o 5.5 V. 2. Features and benefits  Symmetrical output impedance  High n oise immunity  Low power dissipation  Balanced propagation delays  Mu ltiple package options  ESD.


NXP Semiconductors 74AHC2G126

protection:  HBM JESD22-A114E: excee ds 2000 V  MM JESD22-A115-A: exceeds 200 V  CDM JESD22-C101C: exceeds 10 00 V  Specified from 40 C to + 125 C 3. Ordering information Tabl e 1. Ordering information Type number Package T .


NXP Semiconductors 74AHC2G126

.

Part

74AHC2G126

Description

Dual buffer/line driver



Feature


74AHC2G126; 74AHCT2G126 Dual buffer/lin e driver; 3-state Rev. 7 — 6 May 2013 Product data sheet 1. General descri ption The 74AHC2G126 and 74AHCT2G126 a re high-speed Si-gate CMOS devices. The y provide a dual non-inverting buffer/l ine driver with 3-state output. The 3-s tate output is controlled by the output enable input (nOE). A LOW at nOE cause s the output to assu.
Manufacture

NXP Semiconductors

Datasheet
Download 74AHC2G126 Datasheet




 74AHC2G126
74AHC2G126; 74AHCT2G126
Dual buffer/line driver; 3-state
Rev. 7 — 6 May 2013
Product data sheet
1. General description
The 74AHC2G126 and 74AHCT2G126 are high-speed Si-gate CMOS devices. They
provide a dual non-inverting buffer/line driver with 3-state output. The 3-state output is
controlled by the output enable input (nOE). A LOW at nOE causes the output to assume
a high-impedance OFF-state.
The AHC device has CMOS input switching levels and supply voltage range 2 V to 5.5 V.
The AHCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features and benefits
Symmetrical output impedance
High noise immunity
Low power dissipation
Balanced propagation delays
Multiple package options
ESD protection:
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
Specified from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name Description
74AHC2G126DP
74AHCT2G126DP
40 C to +125 C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
74AHC2G126DC
74AHCT2G126DC
40 C to +125 C VSSOP8 plastic very thin shrink small outline package;
8 leads; body width 2.3 mm
74AHC2G126GD
74AHCT2G126GD
40 C to +125 C XSON8 plastic extremely thin small outline package; no
leads; 8 terminals; body 3 2 0.5 mm
Version
SOT505-2
SOT765-1
SOT996-2




 74AHC2G126
NXP Semiconductors
74AHC2G126; 74AHCT2G126
Dual buffer/line driver; 3-state
4. Marking
Table 2. Marking codes
Type number
74AHC2G126DP
74AHCT2G126DP
74AHC2G126DC
74AHCT2G126DC
74AHC2G126GD
74AHCT2G126GD
Marking[1]
A26
C26
A26
C26
A26
C26
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1A
2
1 1OE
2A
5
7 2OE
1Y
6
2Y
3
mna946
Fig 1. Logic symbol
2
1
1
EN1
5
7
6
3
mna947
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
nA nY
nOE
mna234
Fig 3. Logic diagram (one buffer)
74AHC2G126
74AHCT2G126
1OE 1
1A 2
2Y 3
GND 4
8 VCC
7 2OE
6 1Y
5 2A
001aaj262
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
74AHC2G126
74AHCT2G126
1OE 1
1A 2
8 VCC
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aaj263
Transparent top view
Fig 5. Pin configuration SOT996-2 (XSON8)
74AHC_AHCT2G126
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 6 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 16




 74AHC2G126
NXP Semiconductors
74AHC2G126; 74AHCT2G126
Dual buffer/line driver; 3-state
6.2 Pin description
Table 3. Pin description
Symbol
Pin
1OE, 2OE
1, 7
1A, 2A
2, 5
GND
4
1Y, 2Y
6, 3
VCC
8
7. Functional description
Description
output enable input (active HIGH)
data input
ground (0 V)
data output
supply voltage
Table 4.
Control
nOE
H
H
L
Function table[1]
Input
nA
L
H
X
Output
nY
L
H
Z
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC
VI
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
VI < 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
Tamb = 40 C to +125 C
0.5
0.5
[1] 20
[1] -
-
-
75
65
[2] -
+7.0
+7.0
-
20
25
75
-
+150
250
V
V
mA
mA
mA
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 118 C the value of Ptot derates linearly with 7.8 mW/K.
74AHC_AHCT2G126
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 6 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 16



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