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OR gate. 74AHCT2G32 Datasheet

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OR gate. 74AHCT2G32 Datasheet






74AHCT2G32 gate. Datasheet pdf. Equivalent




74AHCT2G32 gate. Datasheet pdf. Equivalent





Part

74AHCT2G32

Description

Dual 2-input OR gate



Feature


74AHC2G32; 74AHCT2G32 Dual 2-input OR g ate Rev. 3 — 14 May 2013 Product dat a sheet 1. General description The 74 AHC2G32; 74AHCT2G32 is a high-speed Si- gate CMOS device. The 74AHC2G32; 74AHCT 2G32 provides two 2-input OR gates. 2. Features and benefits  Symmetrical output impedance  High noise immunit y  ESD protection:  HBM JESD22-A1 14E exceeds 2000 V  MM JESD.
Manufacture

NXP Semiconductors

Datasheet
Download 74AHCT2G32 Datasheet


NXP Semiconductors 74AHCT2G32

74AHCT2G32; 22-A115-A exceeds 200 V  CDM JESD22-C 101C exceeds 1000 V  Low power dissi pation  Balanced propagation delays  Multiple package options  Specif ied from 40 C to +85 C and fro m 40 C to +125 C 3. Ordering information Table 1. Ordering informat ion Type number Package Temperature range Name 74AHC2G32DP 40 C to + 125 C TSSOP8 74AHCT2G32DP 74AHC2G32DC 40.


NXP Semiconductors 74AHCT2G32

C to +125 C VSSOP8 74AHCT2G32DC 74AHC2G32GD 40 C to +125 C XS ON8 74AHCT2G32GD Description Version plastic thin shrink small outline pac kage; 8 leads; body SOT505-2 width 3 mm ; lead length 0.5 mm .


NXP Semiconductors 74AHCT2G32

.

Part

74AHCT2G32

Description

Dual 2-input OR gate



Feature


74AHC2G32; 74AHCT2G32 Dual 2-input OR g ate Rev. 3 — 14 May 2013 Product dat a sheet 1. General description The 74 AHC2G32; 74AHCT2G32 is a high-speed Si- gate CMOS device. The 74AHC2G32; 74AHCT 2G32 provides two 2-input OR gates. 2. Features and benefits  Symmetrical output impedance  High noise immunit y  ESD protection:  HBM JESD22-A1 14E exceeds 2000 V  MM JESD.
Manufacture

NXP Semiconductors

Datasheet
Download 74AHCT2G32 Datasheet




 74AHCT2G32
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
Rev. 3 — 14 May 2013
Product data sheet
1. General description
The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.
The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.
2. Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
HBM JESD22-A114E exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101C exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G32DP 40 C to +125 C TSSOP8
74AHCT2G32DP
74AHC2G32DC 40 C to +125 C VSSOP8
74AHCT2G32DC
74AHC2G32GD 40 C to +125 C XSON8
74AHCT2G32GD
Description
Version
plastic thin shrink small outline package; 8 leads; body SOT505-2
width 3 mm; lead length 0.5 mm
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm




 74AHCT2G32
NXP Semiconductors
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
4. Marking
Table 2. Marking
Type number
74AHC2G32DP
74AHCT2G32DP
74AHC2G32DC
74AHCT2G32DC
74AHC2G32GD
74AHCT2G32GD
Marking code[1]
A32
C32
A32
C32
A32
C32
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1 1A
2 1B
5 2A
6 2B
1Y 7
2Y 3
mna733
Fig 1. Logic symbol
1
1 7
2
5
1 3
6
mna734
Fig 2. IEC logic symbol
6. Pinning information
6.1 Pinning
B
Y
A
mna166
Fig 3. Logic diagram (one gate)
74AHC2G32
74AHCT2G32
1A 1
1B 2
2Y 3
GND 4
8 VCC
7 1Y
6 2B
5 2A
001aaj504
Fig 4. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
74AHC2G32
74AHCT2G32
1A 1
1B 2
8 VCC
7 1Y
2Y 3
6 2B
GND 4
5 2A
001aaj505
Transparent top view
Fig 5. Pin configuration SOT996-2 (XSON8)
74AHC_AHCT2G32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 14




 74AHCT2G32
NXP Semiconductors
74AHC2G32; 74AHCT2G32
Dual 2-input OR gate
6.2 Pin description
Table 3.
Symbol
1A, 2A
1B, 2B
GND
1Y, 2Y
VCC
Pin description
Pin
1, 5
2, 6
4
7, 3
8
7. Functional description
Description
data input
data input
ground (0 V)
data output
supply voltage
Table 4.
Input
nA
L
L
H
H
Function table[1]
nB
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level.
8. Limiting values
Output
nY
L
H
H
H
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
VI input voltage
IIK
input clamping current
VI < 0.5 V
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
0.5
0.5
[1] 20
[1] -
+7.0
+7.0
-
20
V
V
mA
mA
IO output current
0.5 V < VO < VCC + 0.5 V
- 25 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
Tamb = 40 C to +125 C
-
75
65
[2] -
75
-
+150
250
mA
mA
C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 C the value of Ptot derates linearly with 8 mW/K.
For XSON8 package: above 45 C the value of Ptot derates linearly with 2.4 mW/K.
74AHC_AHCT2G32
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 14 May 2013
© NXP B.V. 2013. All rights reserved.
3 of 14



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