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Clock Generator/Synchronizer. AD9548 Datasheet

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Clock Generator/Synchronizer. AD9548 Datasheet






AD9548 Generator/Synchronizer. Datasheet pdf. Equivalent




AD9548 Generator/Synchronizer. Datasheet pdf. Equivalent





Part

AD9548

Description

Quad/Octal Input Network Clock Generator/Synchronizer



Feature


Data Sheet Quad/Octal Input Network Clo ck Generator/Synchronizer AD9548 FEATU RES APPLICATIONS Supports Stratum 2 s tability in holdover mode Supports refe rence switchover with phase build-out S upports hitless reference switchover Au to/manual holdover and reference switch over 4 pairs of reference input pins wi th each pair configurable as a single d ifferential input .
Manufacture

Analog Devices

Datasheet
Download AD9548 Datasheet


Analog Devices AD9548

AD9548; or as 2 independent singleended inputs I nput reference frequencies from 1 Hz to 750 MHz Reference validation and frequ ency monitoring (1 ppm) Programmable in put reference switchover priority 30-bi t programmable input reference divider 4 pairs of clock output pins with each pair configurable as a single different ial LVDS/LVPECL output or as 2 singleen ded CMOS outputs O.


Analog Devices AD9548

utput frequencies up to 450 MHz 30-bit i nteger and 10-bit fractional programmab le feedback divider Programmable digita l loop filter covering loop bandwidths from 0.001 Hz to 100 kHz Optional low n oise LC-VCO system clock multiplier Opt ional crystal resonator for system cloc k input On-chip EEPROM to store multipl e power-up profiles Software controlled power-down 88-lea.


Analog Devices AD9548

d LFCSP package Network synchronization Cleanup of reference clock jitter GPS 1 pulse per second synchronization SONE T/SDH clocks up to OC-192, including FE C Stratum 2 holdover, jitter cleanup, a nd phase transient control Stratum 3E a nd Stratum 3 reference clocks Wireless base station controllers Cable infrastr ucture Data communications GENERAL DESC RIPTION The AD9548.

Part

AD9548

Description

Quad/Octal Input Network Clock Generator/Synchronizer



Feature


Data Sheet Quad/Octal Input Network Clo ck Generator/Synchronizer AD9548 FEATU RES APPLICATIONS Supports Stratum 2 s tability in holdover mode Supports refe rence switchover with phase build-out S upports hitless reference switchover Au to/manual holdover and reference switch over 4 pairs of reference input pins wi th each pair configurable as a single d ifferential input .
Manufacture

Analog Devices

Datasheet
Download AD9548 Datasheet




 AD9548
Data Sheet
Quad/Octal Input Network Clock
Generator/Synchronizer
AD9548
FEATURES
APPLICATIONS
Supports Stratum 2 stability in holdover mode
Supports reference switchover with phase build-out
Supports hitless reference switchover
Auto/manual holdover and reference switchover
4 pairs of reference input pins with each pair configurable as
a single differential input or as 2 independent single-
ended inputs
Input reference frequencies from 1 Hz to 750 MHz
Reference validation and frequency monitoring (1 ppm)
Programmable input reference switchover priority
30-bit programmable input reference divider
4 pairs of clock output pins with each pair configurable as a
single differential LVDS/LVPECL output or as 2 single-
ended CMOS outputs
Output frequencies up to 450 MHz
30-bit integer and 10-bit fractional programmable feedback
divider
Programmable digital loop filter covering loop bandwidths
from 0.001 Hz to 100 kHz
Optional low noise LC-VCO system clock multiplier
Optional crystal resonator for system clock input
On-chip EEPROM to store multiple power-up profiles
Software controlled power-down
88-lead LFCSP package
Network synchronization
Cleanup of reference clock jitter
GPS 1 pulse per second synchronization
SONET/SDH clocks up to OC-192, including FEC
Stratum 2 holdover, jitter cleanup, and phase transient
control
Stratum 3E and Stratum 3 reference clocks
Wireless base station controllers
Cable infrastructure
Data communications
GENERAL DESCRIPTION
The AD9548 provides synchronization for many systems,
including synchronous optical networks (SONET/SDH). The
AD9548 generates an output clock synchronized to one of up to
four differential or eight single-ended external input references.
The digital PLL allows for reduction of input time jitter or phase
noise associated with the external references. The AD9548
continuously generates a clean (low jitter), valid output clock
even when all references have failed by means of a digitally
controlled loop and holdover circuitry.
The AD9548 operates over an industrial temperature range of
−40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
STABLE
SOURCE
ANALOG
FILTER
CLOCK
MULTIPLIER
REFERENCE INPUTS
AND
MONITOR MUX
AD9548
DIGITAL
PLL
DAC
SYNC
CLOCK DISTRIBUTION
CHANNEL 0
DIVIDER
CHANNEL 1
DIVIDER
CHANNEL 2
DIVIDER
CHANNEL 3
DIVIDER
SERIAL CONTROL INTERFACE
(SPI or I2C)
EEPROM
STATUS AND
CONTROL PINS
Figure 1.
Rev. G
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Technical Support
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 AD9548
AD9548* Product Page Quick Links
Last Content Update: 08/30/2016
Comparable Parts
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Evaluation Kits
• AD9548 Evaluation Board
• FPGA Mezzanine Card for Wireless Communications
Documentation
Application Notes
• AN-1002: The AD9548 as a GPS Disciplined Stratum 2
Clock
• AN-1061: Behavior of the AD9548 Phase and Frequency
Lock Detectors in the Presence of Random Jitter
• AN-1064: Understanding the Input Reference Monitors of
the AD9548
• AN-1079: Determining the Maximum Tolerable Frequency
Drift Rate of the AD9548 System Clock in Low Loop
Bandwidth Applications
Data Sheet
• AD9548: Quad/Octal Input Network Clock Generator/
Synchronizer Data Sheet
User Guides
• UG-639: Evaluating the AD9547 and AD9548 Digital PLL
Clock Synthesizers
Tools and Simulations
• AD9548 IBIS Models
Reference Materials
Product Selection Guide
• RF Source Booklet
Technical Articles
• Synchronizing NxN MIMO Basestations to an External
Timing Reference
Design Resources
• AD9548 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
View all AD9548 EngineerZone Discussions
Sample and Buy
Visit the product page to see pricing options
Technical Support
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 AD9548
AD9548
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 
Applications....................................................................................... 1 
General Description ......................................................................... 1 
Functional Block Diagram .............................................................. 1 
Revision History ............................................................................... 3 
Specifications..................................................................................... 4 
Supply Voltage............................................................................... 4 
Supply Current.............................................................................. 4 
Power Dissipation......................................................................... 4 
Logic Inputs (M7 to M0, RESET, TDI, TCLK, TMS) .............. 5 
Logic Outputs (M7 to M0, IRQ, TDO) ..................................... 5 
System Clock Inputs (SYSCLKP/SYSCLKN) ........................... 5 
Distribution Clock Inputs (CLKINP/CLKINN) ...................... 6 
Reference Inputs (REFA/REFAA to REFD/REFDD) .............. 7 
Reference Monitors ...................................................................... 7 
Reference Switchover Specifications.......................................... 8 
Distribution Clock Outputs (OUT0 to OUT3) ........................ 8 
DAC Output Characteristics (DACOUTP/DACOUTN) ....... 9 
Time Duration of Digital Functions ........................................ 10 
Digital PLL .................................................................................. 10 
Digital PLL Lock Detection ...................................................... 10 
Holdover Specifications............................................................. 10 
Serial Port Specifications—SPI Mode...................................... 11 
Serial Port Specifications—I2C Mode ...................................... 11 
Jitter Generation ......................................................................... 12 
Absolute Maximum Ratings.......................................................... 14 
ESD Caution................................................................................ 14 
Pin Configuration and Function Descriptions........................... 15 
Typical Performance Characteristics ........................................... 18 
Input/Output Termination Recommendations .......................... 23 
Getting Started ................................................................................ 24 
Power-On Reset .......................................................................... 24 
Initial M0 to M7 Pin Programming......................................... 24 
Device Register Programming.................................................. 24 
Theory of Operation ...................................................................... 26 
Overview...................................................................................... 26 
Reference Clock Inputs.............................................................. 27 
Reference Monitors .................................................................... 27 
Reference Profiles ....................................................................... 28 
Reference Switchover ................................................................. 30 
Digital PLL (DPLL) Core .......................................................... 32 
Direct Digital Synthesizer ......................................................... 34 
Tuning Word Processing ........................................................... 35 
Loop Control State Machine..................................................... 36 
System Clock Inputs................................................................... 37 
SYSCLK PLL Multiplier............................................................. 38 
Clock Distribution ..................................................................... 40 
Status and Control.......................................................................... 44 
Multifunction Pins (M0 to M7) ............................................... 44 
IRQ Pin ........................................................................................ 45 
Watchdog Timer......................................................................... 46 
EEPROM ..................................................................................... 46 
Serial Control Port ......................................................................... 51 
SPI/I2C Port Selection................................................................ 51 
SPI Serial Port Operation.......................................................... 51 
I2C Serial Port Operation .......................................................... 56 
Input/Output Programming Registers ........................................ 59 
Buffered/Active Registers.......................................................... 59 
Autoclear Registers ...................................................................... 59 
Register Access Restrictions ........................................................ 59 
Register Map ................................................................................... 60 
Register Map Bit Descriptions ...................................................... 70 
Serial Port Configuration (Register 0x0000 to
Register 0x0005) ......................................................................... 70 
System Clock (Register 0x0100 to Register 0x0108) ............. 71 
General Configuration (Register 0x0200 to Register 0x0214) .. 72 
DPLL Configuration (Register 0x0300 to Register 0x031B) 75 
Clock Distribution Output Configuration (Register 0x0400 to
Register 0x0419)........................................................................... 77 
Reference Input Configuration (Register 0x0500 to
Register 0x0507) ......................................................................... 81 
Profile Registers (Register 0x0600 to Register 0x07FF) ........ 83 
Operational Controls (Register 0x0A00 to Register 0x0A10)... 92 
Clock Part Serial ID (Register 0x0C00 to Register 0x0C07) 97 
Status Readback (Register 0x0D00 to Register 0x0D19) ...... 97 
Nonvolatile Memory (EEPROM) Control (Register 0x0E00 to
Register 0x0E03) ........................................................................ 101 
EEPROM Storage Sequence (Register 0x0E10 to
Register 0x0E3F)........................................................................ 101 
Power Supply Partitions............................................................... 106 
3.3 V Supplies............................................................................ 106 
Rev. G | Page 2 of 111






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