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Audio Processor. ADAU1445 Datasheet

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Audio Processor. ADAU1445 Datasheet






ADAU1445 Processor. Datasheet pdf. Equivalent




ADAU1445 Processor. Datasheet pdf. Equivalent





Part

ADAU1445

Description

Digital Audio Processor



Feature


Data Sheet SigmaDSP Digital Audio Proce ssor with Flexible Audio Routing Matrix ADAU1442/ADAU1445/ADAU1446 FEATURES F ully programmable audio digital signal processor (DSP) for enhanced sound proc essing Features SigmaStudio, a propriet ary graphical programming tool for the development of custom signal flows 172 MHz SigmaDSP core; 3584 instructions pe r sample at 48 kHz.
Manufacture

Analog Devices

Datasheet
Download ADAU1445 Datasheet


Analog Devices ADAU1445

ADAU1445; 4k parameter RAM, 8k data RAM Flexible audio routing matrix (FARM) 24-channel digital input and output Up to 8 stereo asynchronous sample rate converters (f rom 1:8 up to 7.75:1 ratio and 139 dB D NR) Stereo S/PDIF input and output Supp orts serial and TDM I/O, up to fS = 192 kHz Multichannel byte-addressable TDM serial port Pool of 170 ms digital audi o delay (at 48 kHz.


Analog Devices ADAU1445

) Clock oscillator for generating master clock from crystal PLL for generating core clock from common audio clocks I2 C and SPI control interfaces Standalone operation Self-boot from serial EEPROM 4-channel, 10-bit auxiliary control AD C Multipurpose pins for digital control s and outputs Easy implementation of av ailable third-party algorithms On-chip regulator for gene.


Analog Devices ADAU1445

rating 1.8 V from 3.3 V supply 100-lead TQFP and LQFP packages Temperature rang e: −40°C to +105°C APPLICATIONS Aut omotive audio processing Head units Nav igation systems Rear-seat entertainment systems DSP amplifiers (sound system a mplifiers) Commercial audio processing FUNCTIONAL BLOCK DIAGRAM MP[3:0]/ SPI /I2C* SELFBOOT MP[11:4] ADC[3:0] XTALI XTALO ADAU1442/ ADAU.

Part

ADAU1445

Description

Digital Audio Processor



Feature


Data Sheet SigmaDSP Digital Audio Proce ssor with Flexible Audio Routing Matrix ADAU1442/ADAU1445/ADAU1446 FEATURES F ully programmable audio digital signal processor (DSP) for enhanced sound proc essing Features SigmaStudio, a propriet ary graphical programming tool for the development of custom signal flows 172 MHz SigmaDSP core; 3584 instructions pe r sample at 48 kHz.
Manufacture

Analog Devices

Datasheet
Download ADAU1445 Datasheet




 ADAU1445
Data Sheet
SigmaDSP Digital Audio Processor
with Flexible Audio Routing Matrix
ADAU1442/ADAU1445/ADAU1446
FEATURES
Fully programmable audio digital signal processor (DSP) for
enhanced sound processing
Features SigmaStudio, a proprietary graphical programming
tool for the development of custom signal flows
172 MHz SigmaDSP core; 3584 instructions per sample at 48 kHz
4k parameter RAM, 8k data RAM
Flexible audio routing matrix (FARM)
24-channel digital input and output
Up to 8 stereo asynchronous sample rate converters
(from 1:8 up to 7.75:1 ratio and 139 dB DNR)
Stereo S/PDIF input and output
Supports serial and TDM I/O, up to fS = 192 kHz
Multichannel byte-addressable TDM serial port
Pool of 170 ms digital audio delay (at 48 kHz)
Clock oscillator for generating master clock from crystal
PLL for generating core clock from common audio clocks
I2C and SPI control interfaces
Standalone operation
Self-boot from serial EEPROM
4-channel, 10-bit auxiliary control ADC
Multipurpose pins for digital controls and outputs
Easy implementation of available third-party algorithms
On-chip regulator for generating 1.8 V from 3.3 V supply
100-lead TQFP and LQFP packages
Temperature range: −40°C to +105°C
APPLICATIONS
Automotive audio processing
Head units
Navigation systems
Rear-seat entertainment systems
DSP amplifiers (sound system amplifiers)
Commercial audio processing
FUNCTIONAL BLOCK DIAGRAM
MP[3:0]/
SPI/I2C* SELFBOOT MP[11:4] ADC[3:0]
XTALI XTALO
ADAU1442/
ADAU1445/
ADAU1446
1.8V
REGULATOR
I2C/SPI CONTROL
INTERFACE
AND SELF-BOOT
MP/
AUX ADC
CLOCK
PLL OSCILLATOR
CLKOUT
SPDIFI
SDATA_IN[8:0]
(24-CHANNEL
DIGITAL AUDIO
INPUT)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
S/PDIF
RECEIVER
PROGRAMMABLE AUDIO
PROCESSOR CORE
S/PDIF
TRANSMITTER
FLEXIBLE AUDIO ROUTING MATRIX
(FARM)
SERIAL DATA
INPUT PORT
(×9)
UP TO 16 CHANNELS OF
ASYNCHRONOUS
SAMPLE RATE
CONVERTERS
SERIAL DATA
OUTPUT PORT
(×9)
SERIAL CLOCK
DOMAINS
(×12)
SPDIFO
SDATA_OUT[8:0]
(24-CHANNEL
DIGITAL AUDIO
OUTPUT)
BIT CLOCK
(BCLK)
FRAME CLOCK
(LRCLK)
*SPI/I2C = THE ADDR0, CLATCH, SCL/CCLK, SDA/COUT, AND ADDR1/CDATA PINS.
THERE ARE 12 BIT CLOCKS (BCLK[11:0]) AND 12 FRAME CLOCKS (LRCLK[11:0]) IN TOTAL. OF THE 12 CLOCKS,
SIX ARE ASSIGNABLE, THREE MUST BE OUTPUTS, AND THREE MUST BE INPUTS.
Figure 1.
Rev. D
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license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2010–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com




 ADAU1445
ADAU1442/ADAU1445/ADAU1446
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 4
Specifications..................................................................................... 5
Digital Timing Specifications ..................................................... 8
Absolute Maximum Ratings.......................................................... 11
Thermal Resistance .................................................................... 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Theory of Operation ...................................................................... 17
System Block Diagram............................................................... 17
Overview...................................................................................... 18
Initialization ................................................................................ 20
Master Clock and PLL ............................................................... 21
Voltage Regulator ....................................................................... 25
SRC Group Delay ....................................................................... 25
Control Port ................................................................................ 26
Serial Data Input/Output........................................................... 31
Serial Input Ports ........................................................................ 37
Serial Input Port Modes and Settings ...................................... 39
Serial Output Ports..................................................................... 41
Serial Output Port Modes and Settings ................................... 42
Flexible Audio Routing Matrix (FARM) ................................. 46
Flexible Audio Routing Matrix Modes and Settings.............. 52
Asynchronous Sample Rate Converters .................................. 58
Data Sheet
ASRC Modes and Settings ........................................................ 58
DSP Core ..................................................................................... 60
DSP Core Modes and Settings.................................................. 61
Reliability Features ..................................................................... 62
RAMs ........................................................................................... 64
S/PDIF Receiver and Transmitter ............................................ 65
S/PDIF Modes and Settings ...................................................... 66
Multipurpose Pins...................................................................... 69
Multipurpose Pins Modes and Settings................................... 69
Auxiliary ADC............................................................................ 70
Auxiliary ADC Modes and Settings ........................................ 70
Interfacing with Other Devices .................................................... 71
Drive Strength Modes and Settings ......................................... 71
Flexible TDM Modes ..................................................................... 76
Serial Input Flexible TDM Interface Modes and Settings..... 76
Serial Output Flexible TDM Interface Modes and Settings . 78
Software Features............................................................................ 81
Software Safeload ....................................................................... 81
Software Slew .............................................................................. 81
Global RAM and Register Map .................................................... 82
Overview of Register Address Map ......................................... 82
Details of Register Address Map .............................................. 82
Applications Information .............................................................. 87
Layout Recommendations ........................................................ 87
Typical Application Schematics................................................ 89
Outline Dimensions ....................................................................... 92
Ordering Guide .......................................................................... 92
Rev. D | Page 2 of 92




 ADAU1445
Data Sheet
REVISION HISTORY
11/13—Rev. C to Rev. D
Changes to Table 7 ..........................................................................14
Changes to Serial Input Flexible TDM Interface Modes and
Settings Section................................................................................76
Change to Figure 63 ........................................................................88
Change to Figure 66 ........................................................................91
9/10—Rev. B to Rev. C
Added Table 1, Renumbered Sequentially .....................................4
Changes to System Initialization Sequence Section ...................20
Changes to Table 12 ........................................................................24
Changes to Figure 20 ......................................................................29
Changes to EEPROM Format Section..........................................30
Changes to Table 26 ........................................................................39
Changes to Table 30 ........................................................................44
Changes to Stereo ASRC[3:0] Lock Status and Mute Register
(Address 0xE101), Stereo ASRC[3:0] Mute Ramp Disable
Register (Address 0xE103), and Stereo ASRC[7:4] Lock Status
and Mute Register (Address 0xE141) Sections .......................58
Changes to Architecture Section and Figure 51..........................60
Changes to Core Run Register (Address 0xE228) Section ........61
Changes to Table 55 ........................................................................66
Changes to Table 59 ........................................................................67
Changes to Multipurpose Pins Section and Table 68 .................69
4/10—Rev. A to Rev. B
Added ADAU1442 ............................................................. Universal
Changes to General Description Section .......................................4
Changes to Table 1 ............................................................................5
Added Table 2; Renumbered Sequentially .....................................6
Changes to Table 4 ..........................................................................11
Changes to Overview Section........................................................16
Changes to Power-Up Sequence Section, System Initialization
Sequence Section, and Table 6...................................................19
Changes to Data Bytes Section ......................................................28
Changes to Serial Clock Domains Section ..................................33
Changes to Flexible Audio Routing Matrix—Input Side Section.....47
Changes to ASRC Input Select Pairs[7:0] Registers
(Address 0xE080 to Address 0xE087) Section ........................52
Changes to ASRC Output Rate Bits (Bits[5:0]) Section ..............54
Changes to Stereo ASRC[3:0] Lock Status and Mute Register
(Address 0xE101) Section............................................................57
Changes to Stereo ASRC[7:4] Lock Status and Mute Register
(Address 0xE141) Section..................................................................58
Changes to S/PDIF Transmitter Section ......................................64
Changes to Multipurpose Pins Section ........................................68
Added Multipurpose Pin Value Registers (Address 0x129A to
Address 0x12A5) Section and Table 66; Renumbered
Sequentially ..................................................................................68
Change to Table 84..........................................................................82
Changes to Ordering Guide...................................................................91
ADAU1442/ADAU1445/ADAU1446
4/09—Rev. 0 to Rev. A
Added ADAU1446 ............................................................. Universal
Added LQFP ....................................................................... Universal
Added Minimum Digital Current (DVDD) of ADAU1446,
Maximum Digital Current (DVDD) of ADAU1446, and
AVDD, DVDD, PVDD During Operation of ADAU1446
Parameters, Table 1 .......................................................................5
Changes to Table 4 ............................................................................9
Changes to Overview Section........................................................16
Change to Table 9............................................................................21
Changes to Voltage Regulator Section .........................................23
Changes to EEPROM Format Section..........................................28
Changes to Serial Clock Domains Section ..................................32
Changes to Flexible Audio Routing Matrix—Input Side Section;
Added Figure 40; Renumbered Sequentially...........................46
Changes to Stereo ASRC Routing Overview Section.................47
Changes to ASRC Input Select Pairs[7:0] Registers (Address 0xE080
to Address 0xE087) Section.......................................................51
Changes to ASRC Output Rate Bits (Bits[5:0]) Section.............53
Changes to Serial Output Data Selector Bits
(Bits[5:0]) Section .......................................................................55
Changes to ASRC Modes and Settings Section...........................56
Added Table 43; Renumbered Sequentially.................................61
Updated Outline Dimensions........................................................90
Changes to Ordering Guide...........................................................90
1/09—Revision 0: Initial Version
Rev. D | Page 3 of 92






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