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Static RAM. CYM1465A Datasheet

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Static RAM. CYM1465A Datasheet
















CYM1465A RAM. Datasheet pdf. Equivalent













Part

CYM1465A

Description

512K x 8 PDIP Static RAM



Feature


65A www.DataSheet4U.com CYM1465A 512K x 8 PDIP Static RAM Features • • • • • • • 4.5V–5.5V oper ation CMOS SRAM for optimum speed and p ower Low active power (165 mW max.) Low standby power (L Version)—(110 µW m ax) 2V data retention (L Version) JEDEC -compatible pinout 32-pin, 0.6-inch-wid e DIP package TTL-compatible inputs and outputs an automatic power-down featur.
Manufacture

Cypress Semiconductor

Datasheet
Download CYM1465A Datasheet


Cypress Semiconductor CYM1465A

CYM1465A; e that reduces power consumption by more than 99% when deselected. Writing to t he SRAM is accomplished when the chip s elect (CS) and write enable (WE) inputs are both LOW. Data on the eight input/ output pins (I/O0 through I/O7) of the device is then written into the memory location specified on the address pins (A0 through A18). Reading from the devi ce is accomplished.


Cypress Semiconductor CYM1465A

by taking chip select (CE) and output e nable (OE) LOW while write enable (WE) remains inactive or HIGH. Under these c onditions, the contents of the memory l ocation specified on the address pins ( A0 through A18) will appear on the eigh t appropriate data input/output pins (I /O0 through I/O7).The eight input/outpu t pins (I/O0 through I/O7) are placed i n a high impedance.


Cypress Semiconductor CYM1465A

state when the device is deselected (CE HIGH), the outputs are disabled (OE HI GH), or during a write operation (CE LO W, and WE LOW). The CYM1465A is availab le in a 32-pin 600-mil wide body PDIP p ackage. Functional Description The CYM 1465A is a high-performance CMOS static RAM organized as 512K words by 8 bits. Easy memory expansion is provided by a n active LOW chip .




Part

CYM1465A

Description

512K x 8 PDIP Static RAM



Feature


65A www.DataSheet4U.com CYM1465A 512K x 8 PDIP Static RAM Features • • • • • • • 4.5V–5.5V oper ation CMOS SRAM for optimum speed and p ower Low active power (165 mW max.) Low standby power (L Version)—(110 µW m ax) 2V data retention (L Version) JEDEC -compatible pinout 32-pin, 0.6-inch-wid e DIP package TTL-compatible inputs and outputs an automatic power-down featur.
Manufacture

Cypress Semiconductor

Datasheet
Download CYM1465A Datasheet




 CYM1465A
65A
www.DataSheet4U.com
CYM1465A
Features
• 4.5V–5.5V operation
• CMOS SRAM for optimum speed and power
• Low active power (165 mW max.)
• Low standby power (L Version)—(110 µW max)
• 2V data retention (L Version)
• JEDEC-compatible pinout
• 32-pin, 0.6-inch-wide DIP package
• TTL-compatible inputs and outputs
Functional Description
The CYM1465A is a high-performance CMOS static RAM or-
ganized as 512K words by 8 bits. Easy memory expansion is
provided by an active LOW chip enable (CE), an active LOW
Output Enable (OE), and three-state drivers. This device has
512K x 8 PDIP Static RAM
an automatic power-down feature that reduces power con-
sumption by more than 99% when deselected.
Writing to the SRAM is accomplished when the chip select
(CS) and write enable (WE) inputs are both LOW. Data on the
eight input/output pins (I/O0 through I/O7) of the device is then
written into the memory location specified on the address pins
(A0 through A18). Reading from the device is accomplished by
taking chip select (CE) and output enable (OE) LOW while
write enable (WE) remains inactive or HIGH. Under these con-
ditions, the contents of the memory location specified on the
address pins (A0 through A18) will appear on the eight appro-
priate data input/output pins (I/O0 through I/O7).The eight in-
put/output pins (I/O0 through I/O7) are placed in a high imped-
ance state when the device is deselected (CE HIGH), the
outputs are disabled (OE HIGH), or during a write operation
(CE LOW, and WE LOW).
The CYM1465A is available in a 32-pin 600-mil wide body
PDIP package.
Logic Block Diagram
A0
A1
A4
A5
A6
A7
A12
A14
A16
A17
CE
WE
OE
INPUT BUFFER
512 x 256 x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (µA)
Pin Configuration
DIP
Top View
A18 1 S
32 VCC
A16 2
A14 3
31 A15
30 A17
A12 4
29 WE
I/O0
A7 5
28 A13
A6 6
27 A8
I/O1
A5 7
A4 8
26 A9
25 A11
I/O2
A3 9
A2 10
24 OE
23 A10
I/O3
A1 11
A0 12
22 CE
21 I/O7
I/O4
I/O0
I/O1
13
14
20 I/O6
19 I/O5
I/O5
I/O2 15
18 I/O4
GND 16
17 I/O3
I/O6
I/O7
CYM1465A-70
70
20
20
CYM1465A-85
85
20
20
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05269 Rev. **
Revised March 15, 2002




 CYM1465A
www.DataSheet4U.com
CYM1465A
Maximum Ratings
DC Input Voltage .............................................-0.5V to +7.0V
(Above which the useful life may be impaired.)
Storage Temperature ................................. –55°C to +150°C
Ambient Temperature with
Power Applied............................................... 10°C to +85°C
Supply Voltage to Ground Potential ............... 0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... 0.5V to +7.0V
Electrical Characteristics Over the Operating Range
Operating Range
Range
Commercial
Industrial
Ambient
Temperature
0°C to +70°C
40°C to +85°C
VCC
5V ± 10%
5V ± 10%
Parameter
Description
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIX Input Load Current
IOZ Output Leakage Current
ICC VCC Operating Supply
Current
ISB1 Automatic CS Power-Down
Current
ISB2 Automatic CS Power-Down
Current
Test Conditions
VCC = Min., IOH = 1.0 mA
VCC = Min., IOL = 2.1 mA
GND < VI < VCC
GND < VO < VCC, Output Disabled
VCC = Max., IOUT = 0 mA, CS < VIL
Max. VCC, CE > VIH,
Min. Duty Cycle = 100%
Max. VCC, CE > VCC - 0.3V,
VIN > VCC - 0.3V or VIN < 0.3V
Capacitance[1]
Parameter
CIN
COUT
Description
Input Capacitance
Output Capacitance
Test Conditions
TA = 25°C, f = 1 MHz,
VCC = 5.0V
CYM1465A
Min. Max.
2.4
0.4
2.2 VCC + 0.3
0.3 0.8
1 +1
1 +1
20
Unit
V
V
V
V
µA
µA
mA
1.5 mA
20 µA
Max.
8
10
Unit
pF
pF
AC Test Loads and Waveforms
5V
OUTPUT
INCLUDING
JIG AND
SCOPE
1.847 k
CL[2]
(a)
1.847 k
5V
OUTPUT
1 k
5 pF
INCLUDING
JIG AND
SCOPE
(b)
1 k
3.0V
GND
< 10 ns
Equivalent to:
OUTPUT
THÉVENIN EQUIVALENT
648
1.76V
ALL INPUT PULSES
90%
10%
90%
10%
<10 ns
Notes:
1. Tested on a sample basis.
2. Test conditions assume signal transition times of 10 ns or less, timing reference levels of 1.5V, input levels of 0 to 3.0V, and output loading of the specified
IOL/IOH and 100-pF load capacitance for 85-, 100-, 120-, and 150-ns speeds. CL = 30 pF for 70-ns speed.
Document #: 38-05269 Rev. **
Page 2 of 7




 CYM1465A
www.DataSheet4U.com
CYM1465A
Switching Characteristics Over the Operating Range[2]
Parameter
READ CYCLE
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCS
tHZCS
tPU
tPD
WRITE CYCLE[4]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
Description
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z[3]
CE LOW to Low Z
CE HIGH to High Z[3]
CE LOW to Power Down
CE HIGH to Power Down
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z[3]
CYM1465A-70
Min.
Max.
70
70
10
70
35
5
25
10
25
0
70
70
60
60
0
0
55
30
0
5
25
CYM1465A-85
Min.
Max.
85
85
10
85
45
5
30
10
30
0
85
85
75
75
0
0
65
35
0
5
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Data Retention Characteristics Over the Operating Range (L Version Only)
Commercial Industrial
Parameter
Description
Test Conditions
Min. Max. Min. Max. Unit
VDR VCC for Retention Data
22 V
ICCDR3
tCDR[5]
tR[5]
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
No Input may exceed
Vcc+0.3V
VDR = 3.0V,
CE > VCC 0.3V,
VIN > VCC 0.3V or
VIN < 0.3V
20 20
00
tRC tRC
µA
ns
ns
Notes:
3. CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured ±500 mV from steady-state voltage.
4. The internal write time of the memory is defined by the overlap of CS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
5. Guaranteed, not tested.
Document #: 38-05269 Rev. **
Page 3 of 7




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