DatasheetsPDF.com

SRAM Module. CYM1471 Datasheet

DatasheetsPDF.com

SRAM Module. CYM1471 Datasheet
















CYM1471 Module. Datasheet pdf. Equivalent













Part

CYM1471

Description

(CYM1471 / CYM1481) 2048k X 8 SRAM Module



Feature


1CY M14 81 fax id: 2006 www.DataSheet4 U.com CYM1471 CYM1481 1024K x 8 SRAM Module 2048K x 8 SRAM Module Features β €’ High-density 8-/16-megabit SRAM modu les β€’ High-speed CMOS SRAMs β€” Acces s time of 70 ns β€’ Low active power β€ ” 605 mW (max.), 2M x 8 β€’ Double-side d SMD technology β€’ TTL-compatible inp uts and outputs β€’ Small footprint SIP β€” PCB layout area of 0.72 sq. in..
Manufacture

Cypress Semiconductor

Datasheet
Download CYM1471 Datasheet


Cypress Semiconductor CYM1471

CYM1471; β€’ 2V data retention (L version) are c onstructed from eight (1471) or sixteen (1481) 128K x 8 SRAMs in plastic surfa ce-mount packages on an epoxy laminate board with pins. On-board decoding sele cts one of the SRAMs from the high-orde r address lines, keeping the remaining devices in standby mode for minimum pow er consumption. An active LOW write ena ble signal (WE) cont.


Cypress Semiconductor CYM1471

rols the writing/reading operation of th e memory. When MS and WE inputs are bot h LOW, data on the eight data input/out put pins is written into the memory loc ation specified on the address pins. Re ading the device is accomplished by sel ecting the device and enabling the outp uts MS and OE active LOW while WE remai ns inactive or HIGH. Under these condit ions, the content .


Cypress Semiconductor CYM1471

of the location addressed by the informa tion on the address pins is present on the eight data input/output pins. The i nput/output pins remain in a high-imped ance state unless the module is selecte d, outputs are enabled, and write enabl e (WE) is HIGH. Functional Description The CYM1471 and CYM1481 are high-perfo rmance 8-megabit and 16-megabit static RAM modules organi.




Part

CYM1471

Description

(CYM1471 / CYM1481) 2048k X 8 SRAM Module



Feature


1CY M14 81 fax id: 2006 www.DataSheet4 U.com CYM1471 CYM1481 1024K x 8 SRAM Module 2048K x 8 SRAM Module Features β €’ High-density 8-/16-megabit SRAM modu les β€’ High-speed CMOS SRAMs β€” Acces s time of 70 ns β€’ Low active power β€ ” 605 mW (max.), 2M x 8 β€’ Double-side d SMD technology β€’ TTL-compatible inp uts and outputs β€’ Small footprint SIP β€” PCB layout area of 0.72 sq. in..
Manufacture

Cypress Semiconductor

Datasheet
Download CYM1471 Datasheet




 CYM1471
fax id: 20061CYM1481
www.DataSheet4U.com
CYM1471
CYM1481
Features
β€’ High-density 8-/16-megabit SRAM modules
β€’ High-speed CMOS SRAMs
β€” Access time of 70 ns
β€’ Low active power
β€” 605 mW (max.), 2M x 8
β€’ Double-sided SMD technology
β€’ TTL-compatible inputs and outputs
β€’ Small footprint SIP
β€” PCB layout area of 0.72 sq. in.
β€’ 2V data retention (L version)
Functional Description
The CYM1471 and CYM1481 are high-performance 8-mega-
bit and 16-megabit static RAM modules organized as 1024K
words (1471) or 2048K words (1481) by 8 bits. These modules
1024K x 8 SRAM Module
2048K x 8 SRAM Module
are constructed from eight (1471) or sixteen (1481) 128K x 8
SRAMs in plastic surface-mount packages on an epoxy lami-
nate board with pins. On-board decoding selects one of the
SRAMs from the high-order address lines, keeping the re-
maining devices in standby mode for minimum power con-
sumption.
An active LOW write enable signal (WE) controls the writ-
ing/reading operation of the memory. When MS and WE inputs
are both LOW, data on the eight data input/output pins is writ-
ten into the memory location specified on the address pins.
Reading the device is accomplished by selecting the device
and enabling the outputs MS and OE active LOW while WE
remains inactive or HIGH. Under these conditions, the content
of the location addressed by the information on the address
pins is present on the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the module is selected, outputs are enabled, and write enable
(WE) is HIGH.
Logic Block Diagram
A0–A16
17
OE
WE
A17–A20
4
1 of 8
DECODER
MS
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
1 of 8
DECODER
128K x 8
SRAM
/
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
128K x 8
SRAM
1471-1
Pin Configuration SIP
Top View
A19
VCC
WE
I/O2
I/O3
I/O0
CYM1471
A1
A2
A3
A4
GND
I/O5
A10
A20 (1481)
A11
A5
A13
A14
MS (1471)
MS
A15
A16
A12
A18
A6
I/O1
GND
A0
A7
A8
A9
I/O7
I/O4
I/O6
A17
8
I/O0–I/O7
VCC
OE
1471-2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Cypress Semiconductor Corporation β€’ 3901 North First Street β€’ San Jose β€’ CA 95134 β€’ 408-943-2600
October 1990 – Revised January 2, 1997




 CYM1471
:
www.DataSheet4U.com
CYM1471
CYM1481
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
CYM1471
CYM1481
70 85 100 120 70 85 100 120
95 95 95 95 110 110 110 110
32 32 32 32 64 64 64 64
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ................................. –55Β°C to +125Β°C
Ambient Temperature with
Power Applied................................................... 0Β°C to +70Β°C
Supply Voltage to Ground Potential ............... –0.3V to +7.0V
DC Voltage Applied to Outputs
in High Z State ............................................... –0.3V to +7.0V
DC Input Voltage ............................................–0.3V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Operating Range
Range
Commercial
Ambient
Temperature
0Β°C to +70Β°C
VCC
5V Β± 10%
Electrical Characteristics Over the Operating Range
Parameter
Description
VOH Output HIGH Voltage
VOL Output LOW Voltage
VIH Input HIGH Voltage
VIL Input LOW Voltage
IIX Input Load Current
IOZ Output Leakage Current
ICC VCC Operating Supply
Current
ISB1 Automatic MS
Power-Down Current
ISB2 Automatic MS
Power-Down Current
Test Conditions
VCC = Min., IOH = –1.0 mA
VCC = Min., IOL = 2.0 mA
GND < VI < VCC
GND < VO < VCC, Output Disabled
VCC = Max., MS < VIL, IOUT = 0 mA
1471
Min. Max.
2.4
0.4
2.2 VCC + 0.3
–0.3
0.8
–20 +20
–20 +20
95
Max. VCC, MS > VIH,
Min. Duty Cycle = 100%
Max. VCC, MS > VCC –
0.2V, VIN > VCC – 0.2V, or
VIN < 0.2V
Standard
L Version
–100, –120
L Version
–85
32
16
250
800
1481
Min. Max.
2.4
0.4
2.2 VCC + 0.3
–0.3 0.8
–20 +20
–20 +20
110
64
32
500
1600
Unit
V
V
V
V
Β΅A
Β΅A
mA
mA
mA
Β΅A
Β΅A
Capacitance[1]
Parameter
Description
CINA
Input Capacitance (A0–16, OE, WE)
CINB
Input Capacitance (A17–20, MS)
COUT
Output Capacitance
Note:
1. Tested on a sample basis.
Test Conditions
TA = 25Β°C, f = 1 MHz,
VCC = 5.0V
CYM1471
Max.
75
25
95
CYM1481
Max.
125
25
165
Unit
pF
pF
pF
2




 CYM1471
:
www.DataSheet4U.com
CYM1471
CYM1481
AC Test Loads and Waveforms
R1 2530 Ω
5V
R1 2530 Ω
5V
OUTPUT
100 pF
R2 OUTPUT
2830Ω
5 pF
R2
2830Ω
INCLUDING
JIG AND
SCOPE
(a)
1471-5
INCLUDING
JIG AND
SCOPE
(b)
1471-3
3.0V
GND
< 10 ns
Equivalent to:
THÉVENIN EQUIVALENT
OUTPUT
1340Ω
2.64V
ALL INPUT PULSES
90%
10%
90%
10%
< 10 ns
1471-4
Switching Characteristics Over the Operating Range[2]
1471-70
1481-70
1471–85
1481–85
1471–100
1481–100
1471–120
1481–120
Parameter
Description
Min Max Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC Read Cycle Time
tAA Address to Data Valid
tOHA
Data Hold from Address Change
tAMS
MS LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low Z
tHZOE
OE HIGH to High Z[3]
tLZMS
MS LOW to Low Z[4]
tHZMS
MS HIGH to High Z[3, 4]
WRITE CYCLE[5]
70 85 100 120 ns
70 85 100 120 ns
5 10 10 10 ns
70 85 100 120 ns
40 45 50 60 ns
5 5 5 5 ns
30 30 35 45 ns
5 10 10 10 ns
30 30 35 45 ns
tWC Write Cycle Time
70 85 100 120 ns
tSMS
MS LOW to Write End
65 75 90 100 ns
tAW Address Set-Up to Write End 65 75 90 100 ns
tHA Address Hold from Write End 5 7 7 7 ns
tSA
Address Set-Up to Write Start
0
5
5
5 ns
tPWE
WE Pulse Width
65 65 75 85 ns
tSD Data Set-Up to Write End
30 35 40 45 ns
tHD
tHZWE
Data Hold from Write End
WE LOW to High Z[3]
0 5 5 5 ns
30 30 35 40 ns
tLZWE
WE HIGH to Low Z
5 5 5 5 ns
Notes:
2. Test conditions assume signal transition time of 10 Β΅s or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, output loading of 1 TTL load, and
100-pF load capacitance.
3. tHZOE, tHZMS, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads and Waveforms. Transition is measured Β±500 mV from steady-state voltage.
4. At any given temperature and voltage condition, tHZMS is less than tLZMS for any given device. These parameters are guaranteed and not 100% tested.
5. The internal write time of the memory is defined by the overlap of MS LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
3




Recommended third-party CYM1471 Datasheet







@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)