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inverter gate. 74AUP1G04 Datasheet

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inverter gate. 74AUP1G04 Datasheet






74AUP1G04 gate. Datasheet pdf. Equivalent




74AUP1G04 gate. Datasheet pdf. Equivalent





Part

74AUP1G04

Description

Low power single inverter gate



Feature


www.DataSheet4U.com 74AUP1G04 Low power single inverter gate Features ■ ■ ■ ■ ■ ■ ■ High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V Power down protection on inputs and outputs Balan ced propagation delays: tPLH ≈ tPHL O perating voltage range: VCC (opr) = 1.2 to 3.6 V Low power dissipation: ICC = 1 µA (max.) at TA = 85 °C Latch-up pe rformance exceeds 300 mA (JESD 78, C.
Manufacture

STMicroelectronics

Datasheet
Download 74AUP1G04 Datasheet


STMicroelectronics 74AUP1G04

74AUP1G04; lass II) ESD performance: – 2000-V Hum an-Body Model (A114-A) – 200-V Machin e Model (A115-A) – 1000-V Charged-Dev ice Model (C101) SOT-665 DFN6L Applica tions ■ ■ Mobile phones Personal d igital assistants (PDAs) Description T he 74AUP1G04 is a low voltage CMOS sing le inverter gate fabricated with sub-mi cron silicon gate and double-layer meta l wiring C2MOS technology. I.


STMicroelectronics 74AUP1G04

t is ideal for 1.2 to 3.6 V operations a nd low power and low noise applications . All inputs and outputs are equipped w ith protection circuits against static discharge, giving them 2kV ESD immunity and transient excess voltage. Table 1 . Device summary Order code 74AUPG04DT R 74AUPG04GTR Package DFN6L (1.2 x 1 mm ) SOT-665 (1.6 x 1.6 mm) Packing Tape a nd reel Tape and r.


STMicroelectronics 74AUP1G04

eel March 2008 Rev 1 1/18 www.st.com 18 www.DataSheet4U.com Pin settings 74AUP1G04 1 1.1 Pin settings Pin conn ection Figure 1. Pin connection (top th rough view) NC A GND 1 2 3 6 5 4 VC C NC B NC A GND 1 2 3 5 VCC 4 B DFN6L SOT-665 CS00092 1.2 Pin descri ption Table 2. DFN pin number 1 2 3 4 5 6 Pin assignment SOT pin number 1 2 3 4 5 Symbol NC A G.

Part

74AUP1G04

Description

Low power single inverter gate



Feature


www.DataSheet4U.com 74AUP1G04 Low power single inverter gate Features ■ ■ ■ ■ ■ ■ ■ High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V Power down protection on inputs and outputs Balan ced propagation delays: tPLH ≈ tPHL O perating voltage range: VCC (opr) = 1.2 to 3.6 V Low power dissipation: ICC = 1 µA (max.) at TA = 85 °C Latch-up pe rformance exceeds 300 mA (JESD 78, C.
Manufacture

STMicroelectronics

Datasheet
Download 74AUP1G04 Datasheet




 74AUP1G04
www.DataSheet4U.com
74AUP1G04
Low power single inverter gate
Features
High speed: tPD = 4.3 ns (max.) at VCC = 2.3 V
Power down protection on inputs and outputs
Balanced propagation delays:
tPLH tPHL
Operating voltage range:
VCC (opr) = 1.2 to 3.6 V
Low power dissipation:
ICC = 1 µA (max.) at TA = 85 °C
Latch-up performance exceeds 300 mA (JESD
78, Class II)
ESD performance:
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
Applications
Mobile phones
Personal digital assistants (PDAs)
DFN6L
SOT-665
Description
The 74AUP1G04 is a low voltage CMOS single
inverter gate fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology. It is ideal for 1.2 to 3.6 V operations
and low power and low noise applications.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2kV ESD immunity and transient excess
voltage.
Table 1. Device summary
Order code
74AUPG04DTR
74AUPG04GTR
March 2008
Package
DFN6L (1.2 x 1 mm)
SOT-665 (1.6 x 1.6 mm)
Rev 1
Packing
Tape and reel
Tape and reel
1/18
www.st.com
18




 74AUP1G04
www.DataSPhienets4Ue.tctoinmgs
1 Pin settings
1.1 Pin connection
Figure 1. Pin connection (top through view)
74AUP1G04
1.2
NC 1
A2
GND 3
6 VCC
5 NC
4B
DFN6L
NC 1
A2
GND 3
5 VCC
4B
SOT-665
CS00092
Pin description
Table 2. Pin assignment
DFN pin
number
SOT pin
number
Symbol
1 1 NC
22A
3 3 GND
44B
5 - NC
6 5 VCC
Name and function
Not connected
Data input
Ground (0V)
Data output
Not connected
Positive supply voltage
2/18




 74AUP1G04
www.DataS7h4eAetU4UP.c1oGm04
1.3 Truth table
Figure 2. Truth table
A
Pin settings
B
Table 3.
Truth table
A
L
H
Figure 3. Input and output equivalent circuit
VCC
Input
Overvoltage
control
ESD
protection
B
H
L
ESD
protection
Output
GND
GND
GND
GND
GND
CS08974
3/18



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