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AND gate. 74AUP1G08 Datasheet

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AND gate. 74AUP1G08 Datasheet






74AUP1G08 gate. Datasheet pdf. Equivalent




74AUP1G08 gate. Datasheet pdf. Equivalent





Part

74AUP1G08

Description

Low-power 2-input AND gate



Feature


www.DataSheet4U.com 74AUP1G08 Low-power 2-input AND gate Rev. 02 — 29 June 2 006 Product data sheet 1. General desc ription The 74AUP1G08 is a high-perform ance, low-power, low-voltage, Si-gate C MOS device, superior to most advanced C MOS compatible TTL families. Schmitt-tr igger action at all inputs makes the ci rcuit tolerant to slower input rise and fall times across t.
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP1G08 Datasheet


NXP Semiconductors 74AUP1G08

74AUP1G08; he entire VCC range from 0.8 V to 3.6 V. This device ensures a very low static and dynamic power consumption across th e entire VCC range from 0.8 V to 3.6 V. This device is fully specified for pa rtial Power-down applications using IOF F. The IOFF circuitry disables the outp ut, preventing the damaging backflow c urrent through the device when it is po wered down. The 74AUP1.


NXP Semiconductors 74AUP1G08

G08 provides the single 2-input AND func tion. 2. Features s Wide supply voltag e range from 0.8 V to 3.6 V s High nois e immunity s Complies with JEDEC standa rds: x JESD8-12 (0.8 V to 1.3 V) x JESD 8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protec tion: x HBM JESD22-A114-C Class 3A. Exc eeds 5000 V x MM J.


NXP Semiconductors 74AUP1G08

ESD22-A115-A exceeds 200 V x CDM JESD22- C101-C exceeds 1000 V s Low static powe r consumption; ICC = 0.9 µA (maximum) s Latch-up performance exceeds 100 mA p er JESD 78 Class II s Inputs accept vol tages up to 3.6 V s Low noise overshoot and undershoot < 10 % of VCC s IOFF ci rcuitry provides partial Power-down mod e operation s Multiple package options s Specified from −40.

Part

74AUP1G08

Description

Low-power 2-input AND gate



Feature


www.DataSheet4U.com 74AUP1G08 Low-power 2-input AND gate Rev. 02 — 29 June 2 006 Product data sheet 1. General desc ription The 74AUP1G08 is a high-perform ance, low-power, low-voltage, Si-gate C MOS device, superior to most advanced C MOS compatible TTL families. Schmitt-tr igger action at all inputs makes the ci rcuit tolerant to slower input rise and fall times across t.
Manufacture

NXP Semiconductors

Datasheet
Download 74AUP1G08 Datasheet




 74AUP1G08
www.DataSheet4U.com
74AUP1G08
Low-power 2-input AND gate
Rev. 02 — 29 June 2006
Product data sheet
1. General description
The 74AUP1G08 is a high-performance, low-power, low-voltage, Si-gate CMOS device,
superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
The 74AUP1G08 provides the single 2-input AND function.
2. Features
s Wide supply voltage range from 0.8 V to 3.6 V
s High noise immunity
s Complies with JEDEC standards:
x JESD8-12 (0.8 V to 1.3 V)
x JESD8-11 (0.9 V to 1.65 V)
x JESD8-7 (1.2 V to 1.95 V)
x JESD8-5 (1.8 V to 2.7 V)
x JESD8-B (2.7 V to 3.6 V)
s ESD protection:
x HBM JESD22-A114-C Class 3A. Exceeds 5000 V
x MM JESD22-A115-A exceeds 200 V
x CDM JESD22-C101-C exceeds 1000 V
s Low static power consumption; ICC = 0.9 µA (maximum)
s Latch-up performance exceeds 100 mA per JESD 78 Class II
s Inputs accept voltages up to 3.6 V
s Low noise overshoot and undershoot < 10 % of VCC
s IOFF circuitry provides partial Power-down mode operation
s Multiple package options
s Specified from 40 °C to +85 °C and 40 °C to +125 °C




 74AUP1G08
www.DPahtaSilhiepest4US.ceommiconductors
74AUP1G08
Low-power 2-input AND gate
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G08GW 40 °C to +125 °C TSSOP5
74AUP1G08GM 40 °C to +125 °C XSON6
74AUP1G08GF 40 °C to +125 °C XSON6
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP1G08GW
74AUP1G08GM
74AUP1G08GF
5. Functional diagram
Marking code
pE
pE
pE
1B
2A
Y4
mna113
Fig 1. Logic symbol
1
&4
2
mna114
Fig 2. IEC logic symbol
A
B
Fig 3. Logic diagram
Y
mna221
74AUP1G08_2
Product data sheet
Rev. 02 — 29 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
2 of 17




 74AUP1G08
74AUP1G08w Pwhiliwps S.emiDconaducttorsa S h e e t 4 U . c o m
Low-power 2-input AND gate
6. Pinning information
6.1 Pinning
74AUP1G08
74AUP1G08
B1
6 VCC
B1
A2
GND 3
5 VCC
4Y
001aaf025
A2
5 n.c.
GND 3
4Y
001aaf026
Transparent top view
Fig 4. Pin configuration SOT353-1 Fig 5. Pin configuration SOT886
(TSSOP5)
(XSON6)
74AUP1G08
B1
A2
6 VCC
5 n.c.
GND 3
4Y
001aaf027
Transparent top view
Fig 6. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
n.c.
VCC
Pin description
Pin
TSSOP5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
7. Functional description
Description
data input B
data input A
ground (0 V)
data output Y
not connected
supply voltage
Table 4.
Input
A
L
L
H
H
Function table[1]
[1] H = HIGH voltage level;
L = LOW voltage level.
B
L
H
L
H
Output
Y
L
L
L
H
74AUP1G08_2
Product data sheet
Rev. 02 — 29 June 2006
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
3 of 17



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