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AND Gate. 74AUP1G09 Datasheet

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AND Gate. 74AUP1G09 Datasheet






74AUP1G09 Gate. Datasheet pdf. Equivalent




74AUP1G09 Gate. Datasheet pdf. Equivalent





Part

74AUP1G09

Description

Low-power 2-input AND Gate



Feature


www.DataSheet4U.com 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 01 — 15 January 2009 Product data she et 1. General description The 74AUP1G0 9 provides the single 2-input AND gate with an open-drain output. The output o f the device is an open-drain and can b e connected to other open-drain outputs to implement active-LOW wired-OR or ac tive-HIGH wired-AND .
Manufacture

NXP

Datasheet
Download 74AUP1G09 Datasheet


NXP 74AUP1G09

74AUP1G09; functions. Schmitt trigger action at all inputs makes the circuit tolerant to s lower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V. This device ensures a very low stati c and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V. This device is fully specified for partial Power-down applications using I OFF. The IOFF circui.


NXP 74AUP1G09

try disables the output, preventing the damaging backflow current through the device when it is powered down. 2. Fea tures I Wide supply voltage range from 0.8 V to 3.6 V I High noise immunity I Complies with JEDEC standards: N JESD8- 12 (0.8 V to 1.3 V) N JESD8-11 (0.9 V t o 1.65 V) N JESD8-7 (1.2 V to 1.95 V) N JESD8-5 (1.8 V to 2.7 V) N JESD8-B (2. 7 V to 3.6 V) I ESD .


NXP 74AUP1G09

protection: N HBM JESD22-A114E exceeds 5 000 V N MM JESD22-A115-A exceeds 200 V N CDM JESD22-C101C exceeds 1000 V I Low static power consumption; ICC = 0.9 µ A (maximum) I Latch-up performance exce eds 100 mA per JESD 78 Class II I Input s accept voltages up to 3.6 V I Low noi se overshoot and undershoot < 10 % of V CC I IOFF circuitry provides partial Po wer-down mode opera.

Part

74AUP1G09

Description

Low-power 2-input AND Gate



Feature


www.DataSheet4U.com 74AUP1G09 Low-power 2-input AND gate with open-drain Rev. 01 — 15 January 2009 Product data she et 1. General description The 74AUP1G0 9 provides the single 2-input AND gate with an open-drain output. The output o f the device is an open-drain and can b e connected to other open-drain outputs to implement active-LOW wired-OR or ac tive-HIGH wired-AND .
Manufacture

NXP

Datasheet
Download 74AUP1G09 Datasheet




 74AUP1G09
www.DataSheet4U.com
74AUP1G09
Low-power 2-input AND gate with open-drain
Rev. 01 — 15 January 2009
Product data sheet
1. General description
The 74AUP1G09 provides the single 2-input AND gate with an open-drain output. The
output of the device is an open-drain and can be connected to other open-drain outputs to
implement active-LOW wired-OR or active-HIGH wired-AND functions.
Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall
times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire
VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through
the device when it is powered down.
2. Features
I Wide supply voltage range from 0.8 V to 3.6 V
I High noise immunity
I Complies with JEDEC standards:
N JESD8-12 (0.8 V to 1.3 V)
N JESD8-11 (0.9 V to 1.65 V)
N JESD8-7 (1.2 V to 1.95 V)
N JESD8-5 (1.8 V to 2.7 V)
N JESD8-B (2.7 V to 3.6 V)
I ESD protection:
N HBM JESD22-A114E exceeds 5000 V
N MM JESD22-A115-A exceeds 200 V
N CDM JESD22-C101C exceeds 1000 V
I Low static power consumption; ICC = 0.9 µA (maximum)
I Latch-up performance exceeds 100 mA per JESD 78 Class II
I Inputs accept voltages up to 3.6 V
I Low noise overshoot and undershoot < 10 % of VCC
I IOFF circuitry provides partial Power-down mode operation
I Multiple package options
I Specified from 40 °C to +85 °C and 40 °C to +125 °C




 74AUP1G09
www.DNatXaSPheSete4Um.coicmonductors
74AUP1G09
Low-power 2-input AND gate with open-drain
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AUP1G09GW 40 °C to +125 °C TSSOP5
74AUP1G09GM 40 °C to +125 °C XSON6
74AUP1G09GF 40 °C to +125 °C XSON6
Description
Version
plastic thin shrink small outline package; 5 leads;
body width 1.25 mm
SOT353-1
plastic extremely thin small outline package; no leads; SOT886
6 terminals; body 1 × 1.45 × 0.5 mm
plastic extremely thin small outline package; no leads; SOT891
6 terminals; body 1 × 1 × 0.5 mm
4. Marking
Table 2. Marking
Type number
74AUP1G09GW
74AUP1G09GM
74AUP1G09GF
5. Functional diagram
Marking code
p9
p9
p9
1
B
2
A
4Y
001aad598
Fig 1. Logic symbol
1 &4
2
001aad599
Fig 2. IEC logic symbol
Y
A
B GND
001aad600
Fig 3. Logic diagram
74AUP1G09_1
Product data sheet
Rev. 01 — 15 January 2009
© NXP B.V. 2009. All rights reserved.
2 of 15




 74AUP1G09
74AUP1G09w NwXPwSem. icoDnduca torts a S h e e t 4 U . c o m
Low-power 2-input AND gate with open-drain
6. Pinning information
6.1 Pinning
74AUP1G09
B1
A2
5 VCC
GND 3
4Y
001aai728
Fig 4. Pin configuration
SOT353-1 (TSSOP5)
74AUP1G09
B1
6 VCC
A2
5 n.c.
GND 3
4Y
001aai729
Transparent top view
Fig 5. Pin configuration SOT886
(XSON6)
74AUP1G09
B1
A2
6 VCC
5 n.c.
GND 3
4Y
001aai730
Transparent top view
Fig 6. Pin configuration SOT891
(XSON6)
6.2 Pin description
Table 3.
Symbol
B
A
GND
Y
n.c.
VCC
Pin description
Pin
TSSOP5
1
2
3
4
-
5
XSON6
1
2
3
4
5
6
7. Functional description
Description
data input
data input
ground (0 V)
data output
not connected
supply voltage
Table 4.
Input
A
L
L
H
H
Function table[1]
B
L
H
L
H
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF state.
Output
Y
L
L
L
Z
74AUP1G09_1
Product data sheet
Rev. 01 — 15 January 2009
© NXP B.V. 2009. All rights reserved.
3 of 15



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