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DDR SDRAM. HY5DU121622ALT Datasheet

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DDR SDRAM. HY5DU121622ALT Datasheet
















HY5DU121622ALT SDRAM. Datasheet pdf. Equivalent













Part

HY5DU121622ALT

Description

512Mb DDR SDRAM



Feature


www.DataSheet4U.com HY5DU12422A(L)T HY5 DU12822A(L)T HY5DU121622A(L)T 512Mb DD R SDRAM HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T This document is a g eneral product description and is subje ct to change without notice. Hynix semi conductor does not assume any responsib ility for use of circuits described. No patent licenses are implied. Rev. 0.0/ Feb. 2003 1 www.D.
Manufacture

Hynix Semiconductor

Datasheet
Download HY5DU121622ALT Datasheet


Hynix Semiconductor HY5DU121622ALT

HY5DU121622ALT; ataSheet4U.com HY5DU12422A(L)T HY5DU128 22A(L)T HY5DU121622A(L)T Revision Hist ory 1. Rev 0.0 (Feb. 19) 1) Datasheet R elease in Preliminary version Rev. 0.0 /Feb. 2003 2 www.DataSheet4U.com HY5 DU12422A(L)T HY5DU12822A(L)T HY5DU12162 2A(L)T DESCRIPTION PRELIMINARY The HY5 DU12422A(L)T, HY5DU12822A(L)T and HY5DU 121622A(L)T are a 536,870,912-bit CMOS Double Data Rate(D.


Hynix Semiconductor HY5DU121622ALT

DR) Synchronous DRAM, ideally suited for the main memory applications which req uires large memory density and high ban dwidth. This Hynix 512Mb DDR SDRAMs off er fully synchronous operations referen ced to both rising and falling edges of the clock. While all addresses and con trol inputs are latched on the rising e dges of the CK (falling edges of the /C K), Data, Data str.


Hynix Semiconductor HY5DU121622ALT

obes and Write data masks inputs are sam pled on both rising and falling edges o f it. The data paths are internally pip elined and 2-bit prefetched to achieve very high bandwidth. All input and outp ut voltage levels are compatible with S STL_2. FEATURES • • • • • • VDD, VDDQ = 2.5V +/- 0.2V All inp uts and outputs are compatible with SST L_2 interface Fully differential.





Part

HY5DU121622ALT

Description

512Mb DDR SDRAM



Feature


www.DataSheet4U.com HY5DU12422A(L)T HY5 DU12822A(L)T HY5DU121622A(L)T 512Mb DD R SDRAM HY5DU12422A(L)T HY5DU12822A(L)T HY5DU121622A(L)T This document is a g eneral product description and is subje ct to change without notice. Hynix semi conductor does not assume any responsib ility for use of circuits described. No patent licenses are implied. Rev. 0.0/ Feb. 2003 1 www.D.
Manufacture

Hynix Semiconductor

Datasheet
Download HY5DU121622ALT Datasheet




 HY5DU121622ALT
www.DataSheet4U.com
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
512Mb DDR SDRAM
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
This document is a general product description and is subject to change without notice. Hynix semiconductor does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Rev. 0.0/Feb. 2003
1




 HY5DU121622ALT
www.DataSheet4U.com
Revision History
1. Rev 0.0 (Feb. 19)
1) Datasheet Release in Preliminary version
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
Rev. 0.0/Feb. 2003
2




 HY5DU121622ALT
www.DataSheet4U.com
DESCRIPTION
HY5DU12422A(L)T
HY5DU12822A(L)T
HY5DU121622A(L)T
PRELIMINARY
The HY5DU12422A(L)T, HY5DU12822A(L)T and HY5DU121622A(L)T are a 536,870,912-bit CMOS Double Data
Rate(DDR) Synchronous DRAM, ideally suited for the main memory applications which requires large memory density
and high bandwidth.
This Hynix 512Mb DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
• VDD, VDDQ = 2.5V +/- 0.2V
• All inputs and outputs are compatible with SSTL_2
interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous - data transaction aligned to
bidirectional data strobe (DQS)
• x16 device has two bytewide data strobes (UDQS,
LDQS) per each x8 I/O
• Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
• On chip DLL align DQ and DQS transition with CK
transition
• DM mask write data-in at the both rising and falling
edges of the data strobe
• All addresses and control inputs except data, data
strobes and data masks latched on the rising edges
of the clock
• Programmable /CAS latency 2 / 2.5/ 3 supported
• Programmable burst length 2 / 4 / 8 with both
sequential and interleave mode
• Internal four bank operations with single pulsed
/RAS
• Auto refresh and self refresh supported
• tRAS lock out function supported
• 8192 refresh cycles / 64ms
• JEDEC standard 400mil 66pin TSOP-II with 0.65mm
pin pitch
• Full and Half strength driver option controlled by
EMRS
ORDERING INFORMATION
Part No.
HY5DU12422A(L)T-X*
HY5DU12822A(L)T-X*
HY5DU121622A(L)T-X*
Configuration
128Mx4
64Mx8
32Mx16
* Note : D of speed indicates DDR400.
Package
400mil
66pin
TSOP-II
OPERATING FREQUENCY
Grade
- D4
- D43
CL3
200MHz
200MHz
Remark
(CL-tRCD-tRP)
DDR400 (3-4-4)
DDR400 (3-3-3)
Rev. 0.0 / Feb. 2003
3




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