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EDD5108AFTA-5B-E. D5108AFTA-5B-E Datasheet

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EDD5108AFTA-5B-E. D5108AFTA-5B-E Datasheet






D5108AFTA-5B-E EDD5108AFTA-5B-E. Datasheet pdf. Equivalent




D5108AFTA-5B-E EDD5108AFTA-5B-E. Datasheet pdf. Equivalent





Part

D5108AFTA-5B-E

Description

EDD5108AFTA-5B-E



Feature


DATA SHEET 512M bits DDR SDRAM EDD5108A FTA (64M words × 8 bits) EDD5116AFTA ( 32M words × 16 bits) Specifications Density: 512M bits • Organization 16M words × 8 bits × 4 banks (EDD5 108AFTA) ⎯ 8M words × 16 bits × 4 b anks (EDD5116AFTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS c ompliant) • Power supply: ⎯ DDR400: VDD, VDDQ = 2.6V ± 0.1V ⎯ DDR333, 266: .
Manufacture

Elpida Memory

Datasheet
Download D5108AFTA-5B-E Datasheet


Elpida Memory D5108AFTA-5B-E

D5108AFTA-5B-E; VDD, VDDQ = 2.5V ± 0.2V • Data rate: 400Mbps/333Mbps/266Mbps (max.) • Four internal banks for concurrent operatio n • Interface: SSTL_2 • Burst lengt hs (BL): 2, 4, 8 • Burst type (BT): Sequential (2, 4, 8) ⎯ Interleave (2, 4, 8) • /CAS Latency (CL): 2, 2.5 , 3 • Precharge: auto precharge optio n for each burst access • Driver stre ngth: normal/weak • Refresh: auto-refre.


Elpida Memory D5108AFTA-5B-E

sh, self-refresh • Refresh cycles: 819 2 cycles/64ms ⎯ Average refresh perio d: 7.8μs • Operating ambient tempera ture range www.DataSheet4U.com ⎯ TA = 0°C to +70°C Features • Double-da ta-rate architecture; two data transfer s per clock cycle • The high-speed da ta transfer is realized by the 2 bits p refetch pipelined architecture • Bi-d irectional data strobe (DQS) is tra.


Elpida Memory D5108AFTA-5B-E

nsmitted /received with data for capturi ng data at the receiver • Data inputs , outputs, and DM are synchronized with DQS • DQS is edge-aligned with data for READs; centeraligned with data for WRITEs • Differential clock inputs (C K and /CK) • DLL aligns DQ and DQS tr ansitions with CK transitions • Comma nds entered on each positive CK edge; d ata and data mask referenced.

Part

D5108AFTA-5B-E

Description

EDD5108AFTA-5B-E



Feature


DATA SHEET 512M bits DDR SDRAM EDD5108A FTA (64M words × 8 bits) EDD5116AFTA ( 32M words × 16 bits) Specifications Density: 512M bits • Organization 16M words × 8 bits × 4 banks (EDD5 108AFTA) ⎯ 8M words × 16 bits × 4 b anks (EDD5116AFTA) • Package: 66-pin plastic TSOP (II) ⎯ Lead-free (RoHS c ompliant) • Power supply: ⎯ DDR400: VDD, VDDQ = 2.6V ± 0.1V ⎯ DDR333, 266: .
Manufacture

Elpida Memory

Datasheet
Download D5108AFTA-5B-E Datasheet




 D5108AFTA-5B-E
DATA SHEET
512M bits DDR SDRAM
EDD5108AFTA (64M words × 8 bits)
EDD5116AFTA (32M words × 16 bits)
Specifications
Density: 512M bits
Organization
16M words × 8 bits × 4 banks (EDD5108AFTA)
8M words × 16 bits × 4 banks (EDD5116AFTA)
Package: 66-pin plastic TSOP (II)
Lead-free (RoHS compliant)
Power supply:
DDR400:
VDD, VDDQ = 2.6V ± 0.1V
DDR333, 266: VDD, VDDQ = 2.5V ± 0.2V
Data rate: 400Mbps/333Mbps/266Mbps (max.)
Four internal banks for concurrent operation
Interface: SSTL_2
Burst lengths (BL): 2, 4, 8
Burst type (BT):
Sequential (2, 4, 8)
Interleave (2, 4, 8)
/CAS Latency (CL): 2, 2.5, 3
Precharge: auto precharge option for each burst
access
Driver strength: normal/weak
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Average refresh period: 7.8μs
Operating ambient temperature range
www.DataSheeTt4AU=.co0m°C to +70°C
Features
Double-data-rate architecture; two data transfers per
clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge; data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Document No. E0699E50 (Ver. 5.0)
Date Published November 2006 (K) Japan
Printed in Japan
URL: http://www.elpida.com
©Elpida Memory, Inc. 2005-2006




 D5108AFTA-5B-E
EDD5108AFTA, EDD5116AFTA
Ordering Information
Part number
EDD5108AFTA-5B-E
EDD5108AFTA-5C-E
EDD5108AFTA-6B-E
EDD5108AFTA-7A-E
EDD5108AFTA-7B-E
EDD5116AFTA-5B-E
EDD5116AFTA-5C-E
EDD5116AFTA-6B-E
EDD5116AFTA-7A-E
EDD5116AFTA-7B-E
Mask
version
F
Organization
(words × bits)
64M × 8
Internal
banks
4
Data rate
Mbps (max.)
400
333
266
32M × 16
400
333
266
JEDEC speed bin
(CL-tRCD-tRP)
DDR400B (3-3-3)
DDR400C (3-4-4)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
DDR400B (3-3-3)
DDR400C (3-4-4)
DDR333B (2.5-3-3)
DDR266A (2-3-3)
DDR266B (2.5-3-3)
Package
66-pin Plastic
TSOP (II)
Part Number
E D D 51 08 A F TA - 5B - E
Elpida Memory
Type
D: Monolithic Device
Product Family
D: DDR SDRAM
Density / Bank
51: 512M / 4-bank
Organization
08: x8
16: x16
Power Supply, Interface
A: 2.5V, SSTL_2
Speed Grade Compatibility
Speed bin
www.DataSDhDeeRt440U0.Bcom
DDR400C
DDR333B
DDR266A
DDR266B
Operating Frequencies
CL2
133MHz
133MHz
133MHz
133MHz
100MHz
CL2.5
166MHz
166MHz
166MHz
133MHz
133MHz
Environment Code
E: Lead Free
(RoHS compliant)
Speed
5B: DDR400B (3-3-3)
5C: DDR400C (3-4-4)
6B: DDR333B (2.5-3-3)
7A: DDR266A (2-3-3)
7B: DDR266B (2.5-3-3)
Package
TA: TSOP (II)
Die Rev.
CL3
200MHz
200MHz
166MHz
133MHz
133MHz
Data Sheet E0699E50 (Ver. 5.0)
2




 D5108AFTA-5B-E
EDD5108AFTA, EDD5116AFTA
Pin Configurations
/xxx indicates active low signal.
VDD VDD
DQ0 DQ0
VDDQ VDDQ
NC DQ1
DQ1 DQ2
VSSQ VSSQ
NC DQ3
DQ2 DQ4
VDDQ VDDQ
NC DQ5
DQ3 DQ6
VSSQ VSSQ
NC DQ7
NC NC
VDDQ VDDQ
NC LDQS
NC NC
VDD VDD
NC NC
NC LDM
/WE /WE
/CAS /CAS
/RAS /RAS
/CS /CS
NC NC
BA0 BA0
BA1 BA1
A10(AP) A10(AP)
A0 A0
A1 A1
A2 A2
A3 A3
VDD VDD
66-pin Plastic TSOP(II)
1 66
2 65
3 64
4 63
5 62
6 61
7 60
8 59
9 58
10 57
11 56
12 55
13 54
14 53
15 52
16 51
17 50
18 49
19 48
20 47
21 46
22 45
23 44
24 43
25 42
26 41
27 40
28 39
29 38
30 37
31 36
32 35
33 34
VSS VSS
DQ15 DQ7
VSSQ VSSQ
DQ14 NC
DQ13 DQ6
VDDQ VDDQ
DQ12 NC
DQ11 DQ5
VSSQ VSSQ
DQ10 NC
DQ9 DQ4
VDDQ VDDQ
DQ8 NC
NC NC
VSSQ VSSQ
UDQS DQS
NC NC
VREF VREF
VSS VSS
UDM DM
/CK /CK
CK CK
CKE CKE
NC NC
A12 A12
A11 A11
A9 A9
A8 A8
A7 A7
A6 A6
A5 A5
A4 A4
VSS VSS
X 16
X8
www.DataSheet4U.com
Pin name
A0 to A12
BA0, BA1
DQ0 to DQ15
DQS, LDQS, UDQS
/CS
/RAS
/CAS
/WE
DM, UDM, LDM
(Top view)
Function
Address inputs
Bank select address
Data-input/output
Input and output data strobe
Chip select
Row address strobe command
Column address strobe command
Write enable
Input mask
Pin name
CK
/CK
CKE
VREF
VDD
VSS
VDDQ
VSSQ
NC
Function
Clock input
Differential Clock input
Clock enable
Input reference voltage
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Data Sheet E0699E50 (Ver. 5.0)
3



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